diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-08-08 18:14:54 +0000 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-08-12 08:16:37 +0000 |
| commit | c15281f91d30db47cbeeaa6077823d604f9cc10e (patch) | |
| tree | 47463492ccae9fe2c00dc4388af5eb3fb2af523d /src/mainboard | |
| parent | a88848907f836d19baa319062237d10c08618f70 (diff) | |
mb/google/rex: Add OC pin programming for USB2 Port 8
This patch adds OC pin programming for USB2 Port 8.
BUG=b:224325352
TEST=Able to build and boot MTLRVP.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic9dcaef5972d6c0e9fe264445ea10fcd9a82619f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66543
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/rex/variants/rex0/overridetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index c38721d363..3231f46568 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -4,6 +4,7 @@ chip soc/intel/meteorlake register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # DCI register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A0 register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth |