summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
authorSridhar Siricilla <sridhar.siricilla@intel.com>2021-12-01 14:33:25 +0530
committerFelix Held <felix-coreboot@felixheld.de>2021-12-23 14:42:28 +0000
commitb647e35119c10099b78609f432a7cb9ad3e7e1e2 (patch)
tree05ac083ee18ac5a3d513d33ae4d6a3366127628a /src/mainboard
parent84cd7c351f1dd1afb08365ec51dad7ed356be848 (diff)
soc/intel/alderlake: Add timestamp for cse_fw_sync
The patch add timestamp around cse_fw_sync(). TEST=Verified on Brya, cbmem -t: 948:starting CSE firmware sync 1,381,577 (45,227) 949:finished CSE firmware sync 1,459,513 (77,936) Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Idba11417e0fc7c18d0d938a4293ec3aff1537fb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Diffstat (limited to 'src/mainboard')
0 files changed, 0 insertions, 0 deletions