diff options
| author | Anil Kumar <anil.kumar.k@intel.com> | 2021-04-08 18:11:01 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-04-28 16:24:41 +0000 |
| commit | b46ec389bd5606327b72142a4a1dcf5d3a271381 (patch) | |
| tree | a1c4c5d769636ce7ed022c629be8f9f7680bd750 /src/mainboard | |
| parent | 3ad24c7137650fe194e9edae55f5d3ce6de0a270 (diff) | |
mb/intel/adlrvp_m: Add UART0 GPIO config for ADL-M RVP
This patch adds UART0 config in early GPIO table
Branch=None
Test=Build coreboot and boot on ADLRVP-M board. Check UART logs
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Ic0cc955a02936b74f44fed55a9f4b8054646681a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52201
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/intel/adlrvp/early_gpio_m.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/early_gpio_m.c b/src/mainboard/intel/adlrvp/early_gpio_m.c index c2570045eb..116d3c6840 100644 --- a/src/mainboard/intel/adlrvp/early_gpio_m.c +++ b/src/mainboard/intel/adlrvp/early_gpio_m.c @@ -13,7 +13,17 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_A8, 1, DEEP), }; +static const struct pad_config early_uart_gpio_table[] = { + /* UART0 RX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* UART0 TX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + void variant_configure_early_gpio_pads(void) { + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) + gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table)); + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); } |