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authorSubrata Banik <subratabanik@google.com>2023-12-20 20:36:05 +0530
committerSubrata Banik <subratabanik@google.com>2023-12-22 12:30:47 +0000
commitb27cfd62b20dd526fc2b7413aac10fbed8e2cb9a (patch)
tree2da3bdb668114989c3bcf1a75253d848c40ab6ee /src/mainboard
parente9b7623028e54265e8eaf1cad2f32721f0767086 (diff)
soc/intel/cmn/block/smm: Clear SPI SYNC_SS before disabling WPD
This patch follows the BWG recommendation (doc 729123) by clearing the SPI SYNC_SS bit before disabling the WPD bit in SPI_BIOS_CONTROL. This prevents boot hangs due to a 3-strike error. Unable to follow this guideline would result into boot hang (3-strike error). BRANCH=firmware-rex-15709.B TEST=Able to build and boot google/rex. Change-Id: I18dbbc92554d803eea38ceb0b936a9da9191cb11 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
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