diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-12-28 13:05:56 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-04 11:48:19 +0000 |
| commit | af4bd5633debc8838b563c3fadd96e2b4b060ab5 (patch) | |
| tree | 6867d466f6e3b7ca8e6077979a404caf7609a747 /src/mainboard | |
| parent | 0b9d186e3dc7c209d0fc26b61db3cd98550b71bd (diff) | |
sb/intel: Use `bool` for PCIe coalescing option
Retype the `pcie_port_coalesce` devicetree options and related variables
to better reflect their bivalue (boolean) nature.
Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60416
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
34 files changed, 34 insertions, 34 deletions
diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index 8f7573a9c7..6ea033ec32 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -32,7 +32,7 @@ chip northbridge/intel/sandybridge register "gen4_dec" = "0x00fc0701" register "gpi7_routing" = "2" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x1" device pci 16.0 on # Management Engine Interface 1 diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 93d37dcac0..0f7d0a87d5 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -38,7 +38,7 @@ chip northbridge/intel/sandybridge register "gen2_dec" = "0x000c0241" register "gen3_dec" = "0x000c0251" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" - register "pcie_port_coalesce" = "0" + register "pcie_port_coalesce" = "false" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x3f" register "superspeed_capable_ports" = "0x0000000f" diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb index 9dcf2b7376..0162547431 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" register "gen4_dec" = "0x0000ff29" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" device pci 1c.0 on end # PCIe Port 1 PCIEX_16_3 device pci 1c.1 on end # PCIe Port 2 RTL8111F diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb index b3b1a1cfad..6979615953 100644 --- a/src/mainboard/compulab/intense_pc/devicetree.cb +++ b/src/mainboard/compulab/intense_pc/devicetree.cb @@ -37,7 +37,7 @@ chip northbridge/intel/sandybridge # FIXME: check gfx register "gen3_dec" = "0x000406f1" register "gen4_dec" = "0x000c06a1" register "gpi7_routing" = "2" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" # Intense PC SATA portmap: # Port 0: internal 2.5" bay diff --git a/src/mainboard/dell/optiplex_9010/devicetree.cb b/src/mainboard/dell/optiplex_9010/devicetree.cb index fd950811a4..ef0a0e3174 100644 --- a/src/mainboard/dell/optiplex_9010/devicetree.cb +++ b/src/mainboard/dell/optiplex_9010/devicetree.cb @@ -28,7 +28,7 @@ chip northbridge/intel/sandybridge register "gen2_dec" = "0x007c0901" register "gen3_dec" = "0x003c07e1" register "gen4_dec" = "0x001c0901" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x7" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index 0570cdca55..ad8e50c4b6 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -33,7 +33,7 @@ chip soc/intel/broadwell register "pcie_port_force_aspm" = "0x10" # Enable port coalescing - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP register "icc_clock_disable" = "0x01220000" diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index 0a92efe70b..cfb48123b4 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -36,7 +36,7 @@ chip soc/intel/broadwell # Force enable ASPM for PCIe Port 3 register "pcie_port_force_aspm" = "0x04" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP register "icc_clock_disable" = "0x013b0000" diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 8c54f6a6d0..8eada25326 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -44,7 +44,7 @@ chip northbridge/intel/haswell register "pcie_port_force_aspm" = "0x10" # Enable port coalescing - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP register "icc_clock_disable" = "0x01220000" diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 725cbd1700..c79526e3c9 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -58,7 +58,7 @@ chip northbridge/intel/sandybridge register "gen2_dec" = "0x00040381" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index 08b2c957c7..e972baabaf 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -38,7 +38,7 @@ chip soc/intel/broadwell register "pcie_port_force_aspm" = "0x10" # Enable port coalescing - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP register "icc_clock_disable" = "0x01220000" diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index fda74da3b8..49c34765c8 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -56,7 +56,7 @@ chip northbridge/intel/sandybridge register "gen2_dec" = "0x00fc0901" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index d748277a07..6850cf2c6d 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -54,7 +54,7 @@ chip northbridge/intel/sandybridge register "gen2_dec" = "0x00040069" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index ad700cee29..b38adaf148 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -61,7 +61,7 @@ chip northbridge/intel/sandybridge register "gen3_dec" = "0x0001C1611" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index 76d04d6d2a..98e48efeef 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -28,7 +28,7 @@ chip northbridge/intel/sandybridge register "gen1_dec" = "0x00fc0601" register "gen2_dec" = "0x00fc0801" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0xf" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb index 3dd88258fa..2bfbacdc15 100644 --- a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb @@ -29,7 +29,7 @@ chip northbridge/intel/sandybridge device pci 00.0 on end # Host bridge chip southbridge/intel/bd82x6x # Intel Cougar or Panther Point PCH - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0" diff --git a/src/mainboard/hp/z220_sff_workstation/devicetree.cb b/src/mainboard/hp/z220_sff_workstation/devicetree.cb index 5204e60133..0de9cfabef 100644 --- a/src/mainboard/hp/z220_sff_workstation/devicetree.cb +++ b/src/mainboard/hp/z220_sff_workstation/devicetree.cb @@ -28,7 +28,7 @@ chip northbridge/intel/sandybridge register "gen1_dec" = "0x00fc0601" register "gen2_dec" = "0x00fc0801" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0xf" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index a878019e8f..31bee5d21f 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -32,7 +32,7 @@ chip northbridge/intel/sandybridge #register "gen4_dec" = "0x00000000" # Disable root port coalescing - register "pcie_port_coalesce" = "0" + register "pcie_port_coalesce" = "false" register "xhci_switchable_ports" = "0x0f" register "superspeed_capable_ports" = "0x0f" diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index 86205f8f84..6c2dabeabb 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -38,7 +38,7 @@ chip northbridge/intel/sandybridge register "gpi13_routing" = "2" register "gpi6_routing" = "2" register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 1, 0, 0, 0 }" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x3b" diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index 3c1fc9e073..14d849def9 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -36,7 +36,7 @@ chip northbridge/intel/sandybridge register "gpi13_routing" = "2" register "gpi7_routing" = "2" register "pcie_hotplug_map" = "{ 0, 1, 0, 1, 0, 0, 0, 0 }" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x5" register "superspeed_capable_ports" = "0x0000000f" diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 457ccbee1b..c934f5fe06 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -55,7 +55,7 @@ chip northbridge/intel/sandybridge register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" # device specific SPI configuration register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 32736a83f2..1d6adaf3a8 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -57,7 +57,7 @@ chip northbridge/intel/sandybridge register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" # device specific SPI configuration register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 112dfe71e7..141faa930c 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -35,7 +35,7 @@ chip northbridge/intel/sandybridge register "gpi13_routing" = "2" register "gpi1_routing" = "2" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x17" register "superspeed_capable_ports" = "0x0000000f" diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 75a65f9000..942f029989 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -58,7 +58,7 @@ chip northbridge/intel/sandybridge register "xhci_overcurrent_mapping" = "0x4000201" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "docking_supported" = "1" register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index a1e24d525b..9c75231efc 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -55,7 +55,7 @@ chip northbridge/intel/sandybridge register "gen4_dec" = "0x0c06a1" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index ffa0b93e53..5cfa207564 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -52,7 +52,7 @@ chip northbridge/intel/sandybridge register "gen4_dec" = "0x0c06a1" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index abe40b19dc..ee8a2e083a 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -55,7 +55,7 @@ chip northbridge/intel/sandybridge register "xhci_overcurrent_mapping" = "0x00000c03" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index 30260b0c13..cbf1141aec 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -57,7 +57,7 @@ chip northbridge/intel/sandybridge register "xhci_overcurrent_mapping" = "0x4000201" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index b239d64dae..923c88bc31 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -55,7 +55,7 @@ chip northbridge/intel/sandybridge register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 1f81311685..30a79162d4 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -58,7 +58,7 @@ chip northbridge/intel/sandybridge register "xhci_overcurrent_mapping" = "0x4000201" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb index 6c97e1f6c7..8e5df5863d 100644 --- a/src/mainboard/msi/ms7707/devicetree.cb +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -19,7 +19,7 @@ chip northbridge/intel/sandybridge register "docking_supported" = "0" register "gen1_dec" = "0x000c0291" register "gen2_dec" = "0x000c0a01" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index 8ba2697475..6cb77e3aab 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -46,7 +46,7 @@ chip northbridge/intel/sandybridge register "gpe0_en" = "0x00800040" # Disable root port coalescing - register "pcie_port_coalesce" = "0" + register "pcie_port_coalesce" = "false" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index 7e5555b181..2291f6141e 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -51,7 +51,7 @@ chip northbridge/intel/sandybridge register "gpe0_en" = "0x00800040" # Disable root port coalescing - register "pcie_port_coalesce" = "0" + register "pcie_port_coalesce" = "false" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 1, 1 }" diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index 876f9207bc..d5f6fda26b 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -14,7 +14,7 @@ chip northbridge/intel/sandybridge chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "gen1_dec" = "0x000c0291" register "gen2_dec" = "0x000c0a01" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" register "spi.opprefixes" = "{ 0x50, 0x06 }" diff --git a/src/mainboard/supermicro/x9scl/devicetree.cb b/src/mainboard/supermicro/x9scl/devicetree.cb index 49fcff5a6d..284d8f3204 100644 --- a/src/mainboard/supermicro/x9scl/devicetree.cb +++ b/src/mainboard/supermicro/x9scl/devicetree.cb @@ -20,7 +20,7 @@ chip northbridge/intel/sandybridge register "gen2_dec" = "0x00fc1641" # WPCM450 SuperIO (0x1600-16ff) register "gen3_dec" = "0x00040ca1" # IPMI KCS (0x0ca0-0ca3) register "gen4_dec" = "0x001c03e1" # 3rd UART (0x03e0-03ff) - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x3f" register "spi_lvscc" = "0x2005" |