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authorYu-Ping Wu <yupingso@chromium.org>2021-04-01 16:11:25 +0800
committerHung-Te Lin <hungte@chromium.org>2021-05-07 10:20:11 +0000
commita21797a51ed06dc9a5bff81a9e50c177e7ac23fa (patch)
treeba79c9c1df6fc72ad1757fb1ebb648ee53b6daf5 /src/mainboard
parentce6fdd458b3b93f36a4589584dc13c317c0aa976 (diff)
mb/google/cherry: configure GPIOs
Configure Chromebook specific GPIOs, including EC_AP_INT, SD_CD, EC_IN_RW, GSC_AP_INT and EN_SPK. Change-Id: Id553f632412af440d21a3b51e017cb74cc27fd22 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52924 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/cherry/bootblock.c3
-rw-r--r--src/mainboard/google/cherry/chromeos.c23
-rw-r--r--src/mainboard/google/cherry/gpio.h18
3 files changed, 43 insertions, 1 deletions
diff --git a/src/mainboard/google/cherry/bootblock.c b/src/mainboard/google/cherry/bootblock.c
index 6f61a8282b..adb87d03d9 100644
--- a/src/mainboard/google/cherry/bootblock.c
+++ b/src/mainboard/google/cherry/bootblock.c
@@ -4,6 +4,8 @@
#include <device/mmio.h>
#include <soc/gpio.h>
+#include "gpio.h"
+
struct pad_func {
u8 pin_id;
u8 func;
@@ -34,4 +36,5 @@ static void nor_set_gpio_pinmux(void)
void bootblock_mainboard_init(void)
{
nor_set_gpio_pinmux();
+ setup_chromeos_gpios();
}
diff --git a/src/mainboard/google/cherry/chromeos.c b/src/mainboard/google/cherry/chromeos.c
index 3f0937f693..f606ba39fd 100644
--- a/src/mainboard/google/cherry/chromeos.c
+++ b/src/mainboard/google/cherry/chromeos.c
@@ -2,10 +2,31 @@
#include <bootmode.h>
#include <boot/coreboot_tables.h>
+#include <gpio.h>
-void fill_lb_gpios(struct lb_gpios *gpios)
+#include "gpio.h"
+
+void setup_chromeos_gpios(void)
{
+ gpio_input(GPIO_WP);
+ gpio_input_pullup(GPIO_EC_AP_INT);
+ gpio_input_pullup(GPIO_SD_CD);
+ gpio_input_pullup(GPIO_EC_IN_RW);
+ gpio_input_pullup(GPIO_GSC_AP_INT);
+ gpio_output(GPIO_EN_SPK, 0);
+ gpio_output(GPIO_RESET, 0);
+}
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ struct lb_gpio chromeos_gpios[] = {
+ {GPIO_EC_AP_INT.id, ACTIVE_LOW, -1, "EC interrupt"},
+ {GPIO_SD_CD.id, ACTIVE_LOW, -1, "SD card detect"},
+ {GPIO_EC_IN_RW.id, ACTIVE_LOW, -1, "EC in RW"},
+ {GPIO_GSC_AP_INT.id, ACTIVE_LOW, -1, "TPM interrupt"},
+ {GPIO_EN_SPK.id, ACTIVE_HIGH, -1, "speaker enable"},
+ };
+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
int get_recovery_mode_switch(void)
diff --git a/src/mainboard/google/cherry/gpio.h b/src/mainboard/google/cherry/gpio.h
new file mode 100644
index 0000000000..28e11869a8
--- /dev/null
+++ b/src/mainboard/google/cherry/gpio.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __MAINBOARD_GOOGLE_CHERRY_GPIO_H__
+#define __MAINBOARD_GOOGLE_CHERRY_GPIO_H__
+
+#include <soc/gpio.h>
+
+#define GPIO_EC_AP_INT GPIO(GPIO_04)
+#define GPIO_WP GPIO(GPIO_05)
+#define GPIO_SD_CD GPIO(I2SO1_D1)
+#define GPIO_EC_IN_RW GPIO(DGI_D10)
+#define GPIO_GSC_AP_INT GPIO(DGI_D11)
+#define GPIO_EN_SPK GPIO(UART1_RTS)
+#define GPIO_RESET GPIO(UART1_CTS)
+
+void setup_chromeos_gpios(void);
+
+#endif