diff options
| author | Nick Vaccaro <nvaccaro@chromium.org> | 2018-01-21 22:11:52 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-01-26 17:24:17 +0000 |
| commit | 9e17e11d8dcd706d7fb8d43e5cf1645efcfc2985 (patch) | |
| tree | a2d16ee6bdac748f0ca38a9402d0443ec2c4d71b /src/mainboard | |
| parent | 25794d2a65049e1427ef04c5944343d11b4b0054 (diff) | |
mainboard/google/zoombini/variant/meowth: add PCH_WP_OD
Configure GPP_H12 as an input for PCH_WP_OD.
BUG=b:72202352
BRANCH=none
TEST=none
Change-Id: Ie5b60644a24d745add4d0d38c1421974b8a0017b
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h | 2 | ||||
| -rw-r--r-- | src/mainboard/google/zoombini/variants/meowth/gpio.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h index ea48e62c57..f1460d2cbf 100644 --- a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h @@ -29,7 +29,7 @@ #define GPIO_EC_IN_RW GPP_A8 /* BIOS Flash Write Protect */ -#define GPIO_PCH_WP GPP_A1 +#define GPIO_PCH_WP GPP_H12 /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK diff --git a/src/mainboard/google/zoombini/variants/meowth/gpio.c b/src/mainboard/google/zoombini/variants/meowth/gpio.c index e0eaa9d259..3e43add685 100644 --- a/src/mainboard/google/zoombini/variants/meowth/gpio.c +++ b/src/mainboard/google/zoombini/variants/meowth/gpio.c @@ -226,7 +226,7 @@ static const struct pad_config gpio_table[] = { NF1), /* PCH_RCAM_SAR0_I2C5_SDA */ /* I2C5_SCL */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), /* PCH_RCAM_SAR0_I2C5_SCL */ -/* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE), +/* M2_SKT2_CFG0 */ PAD_CFG_GPI(GPP_H12, NONE, DEEP), /* PCH_WP_OD */ /* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE), /* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), /* M2_SKT2_CFG3 */ PAD_NC(GPP_H15, NONE), |