diff options
| author | Brenton Dong <brenton.m.dong@intel.com> | 2017-02-15 11:50:02 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-02-22 23:21:37 +0100 |
| commit | 97f542efc285a4a2d7245f75cd5f871f5f60b890 (patch) | |
| tree | e286682a019201059e9039425b1fe32abd31ac76 /src/mainboard | |
| parent | 35f03d902700e5a9d99a561516588169598b0f07 (diff) | |
intel/minnow3: Configure memory properly
Set the proper memory configuration for the MinnowBoard 3. The current
values are copied from intel/leafhill. Set the proper values for
MinnowBoard 3.
Change-Id: Ie37842f5ce2cabaa892f42ee945c91fe3ace527a
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/18374
Tested-by: build bot (Jenkins)
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/intel/minnow3/romstage.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/intel/minnow3/romstage.c b/src/mainboard/intel/minnow3/romstage.c index 5c784ba629..04cdad4a57 100644 --- a/src/mainboard/intel/minnow3/romstage.c +++ b/src/mainboard/intel/minnow3/romstage.c @@ -61,7 +61,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memupd->FspmConfig.InterleavedMode = 0x2; memupd->FspmConfig.ChannelsSlicesEnable = 0x0; memupd->FspmConfig.MinRefRate2xEnable = 0x0; - memupd->FspmConfig.DualRankSupportEnable = 0x1; + memupd->FspmConfig.DualRankSupportEnable = 0x0; memupd->FspmConfig.RmtMode = 0x0; memupd->FspmConfig.MemorySizeLimit = 0x1800; memupd->FspmConfig.LowMemoryMaxValue = 0x0; @@ -69,7 +69,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memupd->FspmConfig.HighMemoryMaxValue = 0x0; memupd->FspmConfig.DIMM0SPDAddress = 0x0; memupd->FspmConfig.DIMM1SPDAddress = 0x0; - memupd->FspmConfig.Ch0_RankEnable = 0x3; + memupd->FspmConfig.Ch0_RankEnable = 0x1; memupd->FspmConfig.Ch0_DeviceWidth = 0x1; memupd->FspmConfig.Ch0_DramDensity = 0x2; memupd->FspmConfig.Ch0_Option = 0x3; @@ -77,7 +77,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memupd->FspmConfig.Ch0_TristateClk1 = 0x0; memupd->FspmConfig.Ch0_Mode2N = 0x0; memupd->FspmConfig.Ch0_OdtLevels = 0x0; - memupd->FspmConfig.Ch1_RankEnable = 0x3; + memupd->FspmConfig.Ch1_RankEnable = 0x1; memupd->FspmConfig.Ch1_DeviceWidth = 0x1; memupd->FspmConfig.Ch1_DramDensity = 0x2; memupd->FspmConfig.Ch1_Option = 0x3; @@ -85,7 +85,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memupd->FspmConfig.Ch1_TristateClk1 = 0x0; memupd->FspmConfig.Ch1_Mode2N = 0x0; memupd->FspmConfig.Ch1_OdtLevels = 0x0; - memupd->FspmConfig.Ch2_RankEnable = 0x3; + memupd->FspmConfig.Ch2_RankEnable = 0x1; memupd->FspmConfig.Ch2_DeviceWidth = 0x1; memupd->FspmConfig.Ch2_DramDensity = 0x2; memupd->FspmConfig.Ch2_Option = 0x3; @@ -93,7 +93,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memupd->FspmConfig.Ch2_TristateClk1 = 0x0; memupd->FspmConfig.Ch2_Mode2N = 0x0; memupd->FspmConfig.Ch2_OdtLevels = 0x0; - memupd->FspmConfig.Ch3_RankEnable = 0x3; + memupd->FspmConfig.Ch3_RankEnable = 0x1; memupd->FspmConfig.Ch3_DeviceWidth = 0x1; memupd->FspmConfig.Ch3_DramDensity = 0x2; memupd->FspmConfig.Ch3_Option = 0x3; |