diff options
| author | Ariel_Fang <ariel_fang@wistron.corp-partner.google.com> | 2021-11-11 17:49:40 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-25 10:43:08 +0000 |
| commit | 7fe266d59d888b24444e6b953d791fb68ccf8807 (patch) | |
| tree | 2d8d386349e1e9c116e3ddec7e43f364eece40d7 /src/mainboard | |
| parent | 3e8ca37b6c4b81615138335f323f24ad9d9f1c6c (diff) | |
mb/google/brya/var/primus: Update thermal table for primus
- Add 4 TEMP_SENSORs
- Configure granularity of power limits
BUG=b:200836803
TEST=USE="project_primus emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Ariel_Fang <ariel_fang@wistron.corp-partner.google.com>
Change-Id: Id4d8dbe678b7f0870aeffa0a0118e65de9d5c22d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/primus/overridetree.cb | 21 |
1 files changed, 14 insertions, 7 deletions
diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index 6a064a7fca..61e24d8ba1 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -78,21 +78,28 @@ chip soc/intel/alderlake device ref dtt on chip drivers/intel/dptf ## sensor information - register "options.tsr[0].desc" = ""DRAM"" - register "options.tsr[1].desc" = ""Charger"" + register "options.tsr[0].desc" = ""SSD"" + register "options.tsr[1].desc" = ""CHARGER"" + register "options.tsr[2].desc" = ""MEMORY"" + register "options.tsr[3].desc" = ""TYPEC"" + # TODO: below values are initial reference values only ## Passive Policy register "policies.passive" = "{ - [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), - [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 5000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 90, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 90, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 90, 5000), }" ## Critical Policy register "policies.critical" = "{ [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), - [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 89, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN), }" register "controls.power_limits" = "{ @@ -101,7 +108,7 @@ chip soc/intel/alderlake .max_power = 15000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 200, + .granularity = 250, }, .pl2 = { .min_power = 55000, |