diff options
| author | Curtis Chen <curtis.chen@intel.com> | 2024-09-21 12:51:43 +0800 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-09-24 05:19:22 +0000 |
| commit | 735ca7f24ad49d416ec7bd8f598e0cdbdf9ae0cc (patch) | |
| tree | bb3c3c64134017090700c20a787fa65e2afe477e /src/mainboard | |
| parent | 2df166f7006db3fc4ffa3995177ea755221d9cd2 (diff) | |
mb/google/rex/{deku,karis}: Enable RTD3 for SSD
Deku S0ix is blocked by the SSD. Enable RTD3 for the SSD to unblock
S0ix. RTD3 for SSDs has already been enabled on Rex and Screebo, too.
To prevent this S0ix blocking issue, RTD3 should also be enabled for
Karis.
BUG=361011799
TEST=Run suspend_stress_test and check whether DUT can enter S0iX.
suspend_stress_test w/o this CL
(with Phison PCIE Gen4 SSD PSENN256GA87FC0)
Suspend failed, s0ix count did not increment from 19182060
Substate Residency
S0i2.0 0
S0i2.1 0
S0i2.2 0
And PC10 residency is only 60% (by SoCWatch)
suspend_stress_test w/ this CL
(with Phison PCIE Gen4 SSD PSENN256GA87FC0)
Substate Residency
S0i2.0 0
S0i2.1 19186
S0i2.2 3389654
And PC10 residency is ~90% (by SoCWatch)
Change-Id: Iaded43a84ad1e245106d36a9d4aa83c40b046649
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84452
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/rex/variants/deku/overridetree.cb | 7 | ||||
| -rw-r--r-- | src/mainboard/google/rex/variants/karis/overridetree.cb | 7 |
2 files changed, 14 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/variants/deku/overridetree.cb b/src/mainboard/google/rex/variants/deku/overridetree.cb index f51a0cd9fe..3b4dce9d6d 100644 --- a/src/mainboard/google/rex/variants/deku/overridetree.cb +++ b/src/mainboard/google/rex/variants/deku/overridetree.cb @@ -167,6 +167,13 @@ chip soc/intel/meteorlake .clk_req = 7, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A19)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A20)" + register "srcclk_pin" = "7" + device generic 0 on end + end end # PCIE11 SSD card device ref tbt_pcie_rp0 on end device ref tbt_pcie_rp1 on end diff --git a/src/mainboard/google/rex/variants/karis/overridetree.cb b/src/mainboard/google/rex/variants/karis/overridetree.cb index d3385f99b3..01447cf4a4 100644 --- a/src/mainboard/google/rex/variants/karis/overridetree.cb +++ b/src/mainboard/google/rex/variants/karis/overridetree.cb @@ -265,6 +265,13 @@ chip soc/intel/meteorlake .clk_req = 8, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A19)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A20)" + register "srcclk_pin" = "8" + device generic 0 on end + end end # PCIE10 SSD card device ref tbt_pcie_rp0 on end device ref tbt_pcie_rp2 on end |