mb/asus/p5gc-mx: Add mainboard

Tested to work:
* GPU (Nvidia gt210) in PCIe x16 slot;
* SATA;
* serial;
* 800MHz and 1067MHz FSB Core 2 Duo CPUs;
* ethernet;
* native VGA graphic init.

What does not work:
* resume from s3 suspend;
* superio hardware monitor (not initialised in coreboot).

Quirks:
* does not boot with just one dimm in slot B.

Change-Id: Ide5494be7f2f16d6b5cfd2ccf4ec438f0587add5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17558
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

18 files changed, 855 insertions, 0 deletions

diff --git a/src/mainboard/asus/p5gc-mx/Kconfig b/src/mainboard/asus/p5gc-mx/Kconfig
new file mode 100644
index 0000000000..6f6eaae03a
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/Kconfig
@@ -0,0 +1,53 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 coresystems GmbH
+## Copyright (C) 2016 Arthur Heymans <arthur@ahemans.xyz
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+if BOARD_ASUS_P5GC_MX
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_X86
+	select CPU_INTEL_SOCKET_LGA775
+	select NORTHBRIDGE_INTEL_I945
+	select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
+	select CHECK_SLFRCS_ON_RESUME
+	select SOUTHBRIDGE_INTEL_I82801GX
+	select SUPERIO_WINBOND_W83627DHG
+	select HAVE_OPTION_TABLE
+	select HAVE_CMOS_DEFAULT
+	select HAVE_MP_TABLE
+	select HAVE_ACPI_TABLES
+	select HAVE_ACPI_RESUME
+	select BOARD_ROMSIZE_KB_512
+	select CHANNEL_XOR_RANDOMIZATION
+	select MAINBOARD_HAS_NATIVE_VGA_INIT
+	select INTEL_EDID
+
+config MAINBOARD_DIR
+	string
+	default asus/p5gc-mx
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "P5GC-MX"
+
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xf0000000
+
+config MAX_CPUS
+	int
+	default 4 ## 2 may be the chipsets limit
+
+endif # BOARD_ASUS_P5GC_MX
diff --git a/src/mainboard/asus/p5gc-mx/Kconfig.name b/src/mainboard/asus/p5gc-mx/Kconfig.name
new file mode 100644
index 0000000000..a325f5841e
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ASUS_P5GC_MX
+	bool "P5GC-MX"
diff --git a/src/mainboard/asus/p5gc-mx/Makefile.inc b/src/mainboard/asus/p5gc-mx/Makefile.inc
new file mode 100644
index 0000000000..f9621db6b3
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/Makefile.inc
@@ -0,0 +1 @@
+ramstage-y += cstates.c
diff --git a/src/mainboard/asus/p5gc-mx/acpi/ec.asl b/src/mainboard/asus/p5gc-mx/acpi/ec.asl
new file mode 100644
index 0000000000..4107d3b60e
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/acpi/ec.asl
@@ -0,0 +1 @@
+/* dummy */
\ No newline at end of file
diff --git a/src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl b/src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl
new file mode 100644
index 0000000000..4aaa33fe74
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* This is board specific information: IRQ routing for the
+ * i945
+ */
+
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// PCIe Graphics		0:1.0
+			Package() { 0x0001ffff, 0, 0, 16 },
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 16 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 16 },
+			Package() { 0x001cffff, 1, 0, 17 },
+			Package() { 0x001cffff, 2, 0, 18 },
+			Package() { 0x001cffff, 3, 0, 19 },
+			// USB and EHCI			0:1d.x
+			Package() { 0x001dffff, 0, 0, 16 },
+			Package() { 0x001dffff, 1, 0, 17 },
+			Package() { 0x001dffff, 2, 0, 18 },
+			Package() { 0x001dffff, 3, 0, 19 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, 0, 16 },
+			Package() { 0x001fffff, 1, 0, 17 },
+			Package() { 0x001fffff, 2, 0, 18 },
+			Package() { 0x001fffff, 3, 0, 19 },
+
+		})
+
+	} Else {
+		Return (Package() {
+			// PCIe Graphics		0:1.0
+			Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+			// USB and EHCI			0:1d.x
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+		})
+	}
+}
diff --git a/src/mainboard/asus/p5gc-mx/acpi/ich7_pci_irqs.asl b/src/mainboard/asus/p5gc-mx/acpi/ich7_pci_irqs.asl
new file mode 100644
index 0000000000..408397bad4
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/acpi/ich7_pci_irqs.asl
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* This is board specific information: IRQ routing for the
+ * 0:1e.0 PCI bridge of the ICH7
+ */
+
+
+If (PICM) {
+	Return (Package() {
+		Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 },
+		Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 },
+		Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 },
+		Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
+		Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x15 },
+		Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x16 },
+		Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x17 },
+		Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x14 },
+		Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 },
+
+	})
+} Else {
+	Return (Package() {
+		Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKB, 0x00 },
+		Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKC, 0x00 },
+		Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKD, 0x00 },
+		Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LPCB.LNKA, 0x00 },
+		Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKF, 0x00 },
+		Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LPCB.LNKG, 0x00 },
+		Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LPCB.LNKH, 0x00 },
+		Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LPCB.LNKE, 0x00 },
+		Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 },
+
+	})
+}
diff --git a/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl b/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl
new file mode 100644
index 0000000000..0454c3fe0a
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Device (SLPB)
+{
+	Name(_HID, EisaId("PNP0C0E"))
+
+	// Wake
+	Name(_PRW, Package(){0x1d, 0x04})
+}
+
+Device (PWRB)
+{
+	Name(_HID, EisaId("PNP0C0C"))
+
+	// Wake
+	Name(_PRW, Package(){0x1d, 0x04})
+}
diff --git a/src/mainboard/asus/p5gc-mx/acpi/superio.asl b/src/mainboard/asus/p5gc-mx/acpi/superio.asl
new file mode 100644
index 0000000000..4107d3b60e
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/acpi/superio.asl
@@ -0,0 +1 @@
+/* dummy */
\ No newline at end of file
diff --git a/src/mainboard/asus/p5gc-mx/acpi/thermal.asl b/src/mainboard/asus/p5gc-mx/acpi/thermal.asl
new file mode 100644
index 0000000000..4107d3b60e
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/acpi/thermal.asl
@@ -0,0 +1 @@
+/* dummy */
\ No newline at end of file
diff --git a/src/mainboard/asus/p5gc-mx/acpi_tables.c b/src/mainboard/asus/p5gc-mx/acpi_tables.c
new file mode 100644
index 0000000000..ca4cde65dd
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/acpi_tables.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+
+#include "southbridge/intel/i82801gx/nvs.h"
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+}
diff --git a/src/mainboard/asus/p5gc-mx/board_info.txt b/src/mainboard/asus/p5gc-mx/board_info.txt
new file mode 100644
index 0000000000..c661268897
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/board_info.txt
@@ -0,0 +1,6 @@
+Category: desktop
+Board URL: https://www.asus.com/Motherboards/P5GCMX/
+Release year: 2007
+ROM package: DIP-8
+ROM protocol: SPI
+ROM socketed: y
diff --git a/src/mainboard/asus/p5gc-mx/cmos.default b/src/mainboard/asus/p5gc-mx/cmos.default
new file mode 100644
index 0000000000..ab7aac1b89
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/cmos.default
@@ -0,0 +1,7 @@
+boot_option=Fallback
+baud_rate=115200
+debug_level=Spew
+hyper_threading=Enable
+nmi=Enable
+boot_devices=''
+gfx_uma_size=8M
\ No newline at end of file
diff --git a/src/mainboard/asus/p5gc-mx/cmos.layout b/src/mainboard/asus/p5gc-mx/cmos.layout
new file mode 100644
index 0000000000..eaf51bb6e6
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/cmos.layout
@@ -0,0 +1,97 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2008 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+# -----------------------------------------------------------------
+entries
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+388          4       h       0        reboot_counter
+#390          2       r       0        unused
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392          3       e       5        baud_rate
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+# coreboot config options: cpu
+400          1       e       2        hyper_threading
+#401          7       r       0        unused
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+
+# coreboot config options: northbridge
+411         3       e       11       gfx_uma_size
+
+# coreboot config options: bootloader
+416        512       s       0        boot_devices
+#928         80       r       0        unused
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+#1000        24       r       0        amd_reserved
+
+# RAM initialization internal data
+1024         8       r       0        C0WL0REOST
+1032         8       r       0        C1WL0REOST
+1040         8       r       0        RCVENMT
+1048         4       r       0        C0DRT1
+1052         4       r       0        C1DRT1
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     1     Emergency
+6     2     Alert
+6     3     Critical
+6     4     Error
+6     5     Warning
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+11    0     1M
+11    1     4M
+11    2     8M
+11    3     16M
+11    4     32M
+11    5     48M
+11    6     64M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/asus/p5gc-mx/cstates.c b/src/mainboard/asus/p5gc-mx/cstates.c
new file mode 100644
index 0000000000..f683756894
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/cstates.c
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <arch/x86/include/arch/acpigen.h>
+
+int get_cst_entries(acpi_cstate_t **entries)
+{
+	return 0;
+}
diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb
new file mode 100644
index 0000000000..7064feb10b
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/devicetree.cb
@@ -0,0 +1,124 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+## Copyright (C) 2016 Arthur Heymans arthur@aheymans.xyz
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+chip northbridge/intel/i945
+
+	device cpu_cluster 0 on
+		chip cpu/intel/socket_LGA775
+			device lapic 0 on end
+		end
+		chip cpu/intel/model_1067x
+			device lapic 0xACAC off end
+		end
+	end
+
+	device domain 0 on
+		device pci 00.0 on # host bridge
+			subsystemid 0x1458 0x5000
+		end
+		device pci 01.0 on # i945 PCIe root port
+			subsystemid 0x1458 0x5000
+			ioapic_irq 2 INTA 0x10
+		end
+		device pci 02.0 on  # vga controller
+			subsystemid 0x1458 0xd000
+			ioapic_irq 2 INTA 0x10
+		end
+
+		chip southbridge/intel/i82801gx
+			register "pirqa_routing" = "0x8b"
+			register "pirqb_routing" = "0x8a"
+			register "pirqc_routing" = "0x86"
+			register "pirqd_routing" = "0x85"
+			register "pirqe_routing" = "0x83"
+			register "pirqf_routing" = "0x80"
+			register "pirqg_routing" = "0x80"
+			register "pirqh_routing" = "0x85"
+
+			register "gpe0_en" = "0"
+
+			register "ide_legacy_combined" = "0x0"
+			register "ide_enable_primary" = "0x1"
+			register "ide_enable_secondary" = "0x0"
+			register "sata_ahci" = "0x0"
+
+			register "p_cnt_throttling_supported" = "0"
+
+			device pci 1b.0 on # High Definition Audio
+				ioapic_irq 2 INTA 0x10
+			end
+			device pci 1c.0 on end # PCIe
+			device pci 1c.1 on end # PCIe
+			#device pci 1c.2 off end # PCIe port 3
+			#device pci 1c.3 off end # PCIe port 4
+			#device pci 1c.4 off end # PCIe port 5
+			#device pci 1c.5 off end # PCIe port 6
+			device pci 1d.0 on # USB UHCI
+				ioapic_irq 2 INTA 0x10
+			end
+			device pci 1d.1 on # USB UHCI
+				ioapic_irq 2 INTB 0x11
+			end
+			device pci 1d.2 on # USB UHCI
+				ioapic_irq 2 INTC 0x12
+			end
+			device pci 1d.3 on # USB UHCI
+				ioapic_irq 2 INTD 0x13
+			end
+			device pci 1d.7 on # USB2 EHCI
+				ioapic_irq 2 INTA 0x10
+			end
+			device pci 1e.0 on end # PCI bridge
+
+			device pci 1f.0 on # LPC bridge
+				ioapic_irq 2 INTA 0x10
+				device pnp 2e.0 on # Floppy
+					io 0x60 = 0x3f0
+					irq 0x70 = 6
+					drq 0x74 = 2
+				end
+				device pnp 2e.1 on # Parallel port
+					io 0x60 = 0x378
+					irq 0x70 = 7
+					drq 0x74 = 3
+				end
+				device pnp 2e.2 on # COM1
+					io 0x60 = 0x3f8
+					irq 0x70 = 4
+				end
+				device pnp 2e.3 on # COM2
+					io 0x60 = 0x2f8
+					irq 0x70 = 3
+				end
+				device pnp 2e.5 on # Keyboard
+					io 0x60 = 0x60
+					io 0x62 = 0x64
+					irq 0x70 = 1 # Keyboard
+					irq 0x72 = 12 # Mouse
+				end
+			end
+			device pci 1f.1 on # IDE
+				ioapic_irq 2 INTB 0x11
+			end
+			device pci 1f.2 on # SATA
+				ioapic_irq 2 INTC 0x12
+			end
+			device pci 1f.3 on # SMBus
+				ioapic_irq 2 INTD 0x13
+			end
+		end
+	end
+end
diff --git a/src/mainboard/asus/p5gc-mx/dsdt.asl b/src/mainboard/asus/p5gc-mx/dsdt.asl
new file mode 100644
index 0000000000..b55aa3fdfb
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/dsdt.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0
+	"COREv4",	// OEM id
+	"COREBOOT",	// OEM table id
+	0x20090419	// OEM revision
+)
+{
+	// Some generic macros
+	/* #include "acpi/platform.asl" */
+
+	// global NVS and variables
+	#include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
+	#include <southbridge/intel/common/acpi/platform.asl>
+
+	// General Purpose Events
+	//#include "acpi/gpe.asl"
+
+	// mainboard specific devices
+	#include "acpi/mainboard.asl"
+
+	// Thermal Zone
+	//#include "acpi/thermal.asl"
+
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <northbridge/intel/i945/acpi/i945.asl>
+			#include <southbridge/intel/i82801gx/acpi/ich7.asl>
+		}
+	}
+
+	/* Chipset specific sleep states */
+	#include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/asus/p5gc-mx/hda_verb.c b/src/mainboard/asus/p5gc-mx/hda_verb.c
new file mode 100644
index 0000000000..a9c25f3593
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/hda_verb.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0883,     /* Vendor ID */
+	0x104382c7,     /* Subsystem ID */
+	0x0000000c,     /* Number of entries */
+
+	/* Pin Widget Verb Table */
+	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+	AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x01a19840),
+	AZALIA_PIN_CFG(0, 0x19, 0x02a19850),
+	AZALIA_PIN_CFG(0, 0x1a, 0x0181304f),
+	AZALIA_PIN_CFG(0, 0x1b, 0x02214020),
+	AZALIA_PIN_CFG(0, 0x1c, 0x593301f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x4005c603),
+	AZALIA_PIN_CFG(0, 0x1e, 0x18561130),
+	AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+};
+
+const u32 pc_beep_verbs[0] = {};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c
new file mode 100644
index 0000000000..9be061f0a8
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/romstage.c
@@ -0,0 +1,275 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2016 Arthur Heymans arthur@aheymans.xyz
+ * Copyright (C) 2016 Kyösti Mälkki <kyosti.malkki@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+// __PRE_RAM__ means: use "unsigned" for device, not a struct.
+
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <lib.h>
+#include <arch/acpi.h>
+#include <cbmem.h>
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627dhg/w83627dhg.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <cpu/x86/bist.h>
+#include <cpu/intel/romstage.h>
+#include <halt.h>
+#include <northbridge/intel/i945/i945.h>
+#include <northbridge/intel/i945/raminit.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+#include <cpu/x86/msr.h>
+#include <cpu/intel/speedstep.h>
+#include <arch/cpu.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
+#define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)
+
+void setup_ich7_gpios(void)
+{
+	/* TODO: This is highly board specific and should be moved */
+	printk(BIOS_DEBUG, " GPIOS...");
+	/* General Registers */
+	outl(0x1f3dffc1, DEFAULT_GPIOBASE + 0x00);	/* GPIO_USE_SEL */
+	outl(0xe0e8f7c2, DEFAULT_GPIOBASE + 0x04);	/* GP_IO_SEL */
+	outl(0xe2febb7e, DEFAULT_GPIOBASE + 0x0c);	/* GP_LVL */
+	/* Output Control Registers */
+	outl(0x00000000, DEFAULT_GPIOBASE + 0x18);	/* GPO_BLINK */
+	/* Input Control Registers */
+	outl(0x00006000, DEFAULT_GPIOBASE + 0x2c);	/* GPI_INV */
+	outl(0x000000ff, DEFAULT_GPIOBASE + 0x30);	/* GPIO_USE_SEL2 */
+	outl(0x000000f0, DEFAULT_GPIOBASE + 0x34);	/* GP_IO_SEL2 */
+	outl(0x00030033, DEFAULT_GPIOBASE + 0x38);	/* GP_LVL2 */
+}
+
+/*
+ * BSEL0 is connected with GPIO32
+ * BSEL1 is connected with GPIO33 with inversed logic
+ * BSEL2 is connected with GPIO55
+ */
+static void setup_sio_gpio(u8 bsel)
+{
+	int need_reset = 0;
+	u8 reg, old_reg;
+
+	pnp_enter_ext_func_mode(GPIO_DEV);
+	pnp_set_logical_device(GPIO_DEV);
+
+	reg = 0x9a;
+	old_reg = pnp_read_config(GPIO_DEV, 0x2c);
+	pnp_write_config(GPIO_DEV, 0x2c, reg);
+	need_reset = (reg != old_reg);
+
+	pnp_write_config(GPIO_DEV, 0x30, 0x0e);
+	pnp_write_config(GPIO_DEV, 0xe0, 0xde);
+	pnp_write_config(GPIO_DEV, 0xf0, 0xf3);
+	pnp_write_config(GPIO_DEV, 0xf4, 0x80);
+	pnp_write_config(GPIO_DEV, 0xf5, 0x80);
+
+	/* Invert GPIO33 */
+	pnp_write_config(GPIO_DEV, 0xf2, 0x08);
+
+	reg = (bsel & 3) << 2;
+	old_reg = pnp_read_config(GPIO_DEV, 0xf1);
+	pnp_write_config(GPIO_DEV, 0xf1, reg);
+	need_reset += ((reg & 0xc) != (old_reg & 0xc));
+
+	reg = (bsel >> 2) << 5;
+	old_reg = pnp_read_config(GPIO_DEV, 0xe1);
+	pnp_write_config(GPIO_DEV, 0xe1, reg);
+	need_reset += ((reg & 0x20) != (old_reg & 0x20));
+
+	pnp_exit_ext_func_mode(GPIO_DEV);
+
+	if (need_reset) {
+		int i = 1000;
+		while (i--)
+			outb(i & 0xff, 0x80);
+		outb(0xe, 0xcf9);
+		halt();
+	}
+}
+
+static u8 msr_get_fsb(void)
+{
+	u8 fsbcfg;
+	msr_t msr;
+	const u32 eax = cpuid_eax(1);
+
+	/* Netburst */
+	if (((eax >> 8) & 0xf) == 0xf) {
+		msr = rdmsr(0x2c);
+		fsbcfg = (msr.lo >> 16) & 0x7;
+	} else { /* Intel Core 2 */
+		msr = rdmsr(MSR_FSB_FREQ);
+		fsbcfg = msr.lo & 0x7;
+	}
+
+	return fsbcfg;
+}
+
+static void ich7_enable_lpc(void)
+{
+	// Enable Serial IRQ
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+	// Set COM1/COM2 decode range
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+	// Enable COM1
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140f);
+	// Enable SuperIO Power Management Events
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0801);
+
+	/* range 0x15e0 - 0x10ef */
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x40291);
+
+
+}
+
+static void rcba_config(void)
+{
+	/* Enable IOAPIC */
+	RCBA8(0x31ff) = 0x03;
+
+	/* Disable unused devices */
+	RCBA32(0x3418) = 0x003c0061;
+
+	/* Enable PCIe Root Port Clock Gate */
+	RCBA32(0x341c) = 0x00000001;
+}
+
+static void early_ich7_init(void)
+{
+	uint8_t reg8;
+	uint32_t reg32;
+
+	// program secondary mlt XXX byte?
+	pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
+
+	// reset rtc power status
+	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
+	reg8 &= ~(1 << 2);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+
+	// usb transient disconnect
+	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
+	reg8 |= (3 << 0);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
+
+	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
+	reg32 |= (1 << 29) | (1 << 17);
+	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
+
+	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
+	reg32 |= (1 << 31) | (1 << 27);
+	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+
+	RCBA32(0x0088) = 0x0011d000;
+	RCBA16(0x01fc) = 0x060f;
+	RCBA32(0x01f4) = 0x86000040;
+	RCBA32(0x0214) = 0x10030509;
+	RCBA32(0x0218) = 0x00020504;
+	RCBA8(0x0220) = 0xc5;
+	reg32 = RCBA32(0x3410);
+	reg32 |= (1 << 6);
+	RCBA32(0x3410) = reg32;
+	reg32 = RCBA32(0x3430);
+	reg32 &= ~(3 << 0);
+	reg32 |= (1 << 0);
+	RCBA32(0x3430) = reg32;
+	RCBA32(0x3418) |= (1 << 0);
+	RCBA16(0x0200) = 0x2008;
+	RCBA8(0x2027) = 0x0d;
+	RCBA16(0x3e08) |= (1 << 7);
+	RCBA16(0x3e48) |= (1 << 7);
+	RCBA32(0x3e0e) |= (1 << 7);
+	RCBA32(0x3e4e) |= (1 << 7);
+
+	// next step only on ich7m b0 and later:
+	reg32 = RCBA32(0x2034);
+	reg32 &= ~(0x0f << 16);
+	reg32 |= (5 << 16);
+	RCBA32(0x2034) = reg32;
+}
+
+void mainboard_romstage_entry(unsigned long bist)
+{
+	int s3resume = 0, boot_mode = 0;
+
+	u8 m_bsel;
+	u8 c_bsel = msr_get_fsb();
+
+	if (bist == 0)
+		enable_lapic();
+
+	ich7_enable_lpc();
+
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+	setup_sio_gpio(c_bsel);
+
+	/* Set up the console */
+	console_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	if (MCHBAR16(SSKPD) == 0xCAFE) {
+		printk(BIOS_DEBUG, "soft reset detected.\n");
+		boot_mode = 1;
+	}
+
+	/* Perform some early chipset initialization required
+	 * before RAM initialization can work
+	 */
+	i945_early_initialization();
+
+	m_bsel = MCHBAR32(CLKCFG) & 7;
+	printk(BIOS_DEBUG, "CPU BSEL: 0x%x\n MCH BSEL: 0x%x\n", c_bsel, m_bsel);
+	if (c_bsel != m_bsel) { /* Should not happen */
+		printk(BIOS_DEBUG, "Setting BSEL straps, resetting...\n");
+		outb(0xe, 0xcf9);
+		halt();
+	}
+
+	s3resume = southbridge_detect_s3_resume();
+
+	/* Enable SPD ROMs and DDR-II DRAM */
+	enable_smbus();
+
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+	dump_spd_registers();
+#endif
+	sdram_initialize(s3resume ? 2 : boot_mode, NULL);
+
+	/* Perform some initialization that must run before stage2 */
+	early_ich7_init();
+
+	/* This should probably go away. Until now it is required
+	 * and mainboard specific
+	 */
+	rcba_config();
+
+	/* Chipset Errata! */
+	fixup_i945_errata();
+
+	/* Initialize the internal PCIe links before we go into stage2 */
+	i945_late_initialization(s3resume);
+}