diff options
| author | Gaggery Tsai <gaggery.tsai@intel.com> | 2018-01-22 11:17:28 +0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2018-01-24 00:44:30 +0000 |
| commit | 63278ab07d684f90804065a6351e0d138f09b507 (patch) | |
| tree | 7d8aa7dd74bdacaf5770b7e1972d52b331307095 /src/mainboard | |
| parent | 94ef4a8a476a66931eb2b2f7f8573fed52956d0f (diff) | |
mb/google/fizz: Add AC/DC loadline settings
This patch adds AC and DC loadline settings since vr_config_enable is
set. Without correct AD/DC loadline settings, VRs reported incorrect
VID values which caused CPU freqency clipping. The clipping reason
could be retrieved from MSR 0x64F. From VRTT report, the AC/DC
loadline resistances are within spec, we can use default value defined
in Table 6-1, doc #543977.
BUG=b:70646304
BRANCH=None
TEST=emerge-fizz coreboot chromeos-bootimage & Read AC/DC loadline
settings from DCI to ensure the values were programmed correctly.
Change-Id: Id0ce29fa5726ca3711aa4c822fb123e2de7bc48f
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23349
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/fizz/devicetree.cb | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index 8cf4e52fb9..9fb366df43 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -116,6 +116,8 @@ chip soc/intel/skylake #| ImonOffset | 0 | 0 | 0 | 0 | #| IccMax | 7A | 34A | 35A | 35A | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m | + #| DcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m | #+----------------+-------+-------+-------+-------+ #Note: IccMax settings are moved to SoC code register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ @@ -128,6 +130,8 @@ chip soc/intel/skylake .imon_slope = 0x0, .imon_offset = 0x0, .voltage_limit = 1520, + .ac_loadline = 1030, + .dc_loadline = 1030, }" register "domain_vr_config[VR_IA_CORE]" = "{ @@ -140,6 +144,8 @@ chip soc/intel/skylake .imon_slope = 0x0, .imon_offset = 0x0, .voltage_limit = 1520, + .ac_loadline = 240, + .dc_loadline = 240, }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ @@ -152,6 +158,8 @@ chip soc/intel/skylake .imon_slope = 0x0, .imon_offset = 0x0, .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, }" register "domain_vr_config[VR_GT_SLICED]" = "{ @@ -164,6 +172,8 @@ chip soc/intel/skylake .imon_slope = 0x0, .imon_offset = 0x0, .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, }" # Enable Root port 3(x1) for LAN. |