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authorRonak Kanabar <ronak.kanabar@intel.com>2020-02-25 14:36:15 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-02-26 05:19:22 +0000
commit4f81bba18b92a04f147611d5b9ec9453b467f65b (patch)
treeb2055a905b6b954fa5d668094f9ecc3bd9c23cc2 /src/mainboard
parent646109a4ea12b28ec5c5cd89c4066bb37835605f (diff)
vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header file for Tiger Lake
Update FSP header file for Tiger Lake platform version 2457. Add SerialIoUartAutoFlow, Enable8254ClockGating, Enable8254ClockGatingOnS3 UPD Change-Id: Ib2a08ce73526fb0eb4e7c2a674af78c2913f0a08 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
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