diff options
| author | Kane Chen <kane_chen@pegatron.corp-partner.google.com> | 2019-10-09 18:07:02 +0800 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2019-11-07 02:08:40 +0000 |
| commit | 46b125ab6bfd5afa72a10eed70af9196e2a8b79c (patch) | |
| tree | 620123d21077594fc646da635cbfd3c54880aa49 /src/mainboard | |
| parent | 2d90cb154706b41481cb3444a44c910266f49b96 (diff) | |
mb/google/hatch/variants/helios: Modify touchscreen power on sequence
The previous values do not affect the touchscreen function. But, the
previous values cause the power leakage in S0ix.
from b/142368161:
1. Modify GPP_D: The specification define T1 >= 10ms. We change it to
12ms for a safety and low impact value in our mind. Enable pin as
GPP_D9 is define to be AVDD in specification. Set it to 10ms to
make it to be the final one to pull low during power off sequence .
2. Add GPP_C4: If we set stop_off_delay_ms to be 1. The true T4 we
got will be 300us . Set stop_off_delay_ms to be 2 . True T4 will be
500us . So we change it to 5 to be a low impact value in our mind
according to the true T4 value we got .
BUG=b:142368161
BRANCH=Master
TEST=emerge-hatch coreboot chromeos-bootimage
./util/abuild/abuild -p none -t google/hatch -x -a
Signed-off-by: YenLu Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I86c920ff1d5c0b510adde8a37f60003072d5f4e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35907
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/hatch/variants/helios/overridetree.cb | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index 262ae8d607..04bf6c12af 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -107,9 +107,13 @@ chip soc/intel/cannonlake register "generic.reset_off_delay_ms" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" - register "generic.enable_delay_ms" = "10" - register "generic.enable_off_delay_ms" = "1" + register "generic.enable_delay_ms" = "12" + register "generic.enable_off_delay_ms" = "10" register "generic.has_power_resource" = "1" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "generic.stop_delay_ms" = "15" + register "generic.stop_off_delay_ms" = "5" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end |