diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-08-23 13:50:32 -0600 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-08-25 14:43:19 +0000 |
| commit | 4610bbc7d0934d85e248b95b70efc788d662d855 (patch) | |
| tree | 836ef6d013e0bda6a39fbd16039bf57015a656a0 /src/mainboard | |
| parent | e7f449386f545d8952f505fe2921bc23be7592a4 (diff) | |
mb/google/brya: Fix PL4 limits
Commit e7f3e6a0558 added PL4 limits for brya0, but the units were mW,
whereas the `tdp_pl4` field is expected to be in whole Watts, therefore
divide all of the settings by 1000.
BUG=b:197468828
TEST=boot brya0 to OS
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6da6bae4eb8c83188d813828cdc4f7c1e20f1b5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/brya/ramstage.c | 5 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/brya0/ramstage.c | 6 |
2 files changed, 7 insertions, 4 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c b/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c index 6504d5b864..d329f4378f 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c @@ -9,6 +9,8 @@ #include <drivers/intel/dptf/chip.h> #include <intelblocks/power_limit.h> +#define MILLIWATTS_TO_WATTS 1000 + void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries) { if (!num_entries) @@ -37,7 +39,8 @@ void variant_update_power_limits(const struct cpu_power_limits *limits, size_t n settings->pl1.max_power = limits[i].pl1_max_power; settings->pl2.min_power = limits[i].pl2_min_power; settings->pl2.max_power = limits[i].pl2_max_power; - soc_config->tdp_pl4 = limits[i].pl4_power; + soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power, + MILLIWATTS_TO_WATTS); printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n", limits[i].pl1_min_power, limits[i].pl1_max_power, diff --git a/src/mainboard/google/brya/variants/brya0/ramstage.c b/src/mainboard/google/brya/variants/brya0/ramstage.c index 9a4fc2825d..d1f399faf1 100644 --- a/src/mainboard/google/brya/variants/brya0/ramstage.c +++ b/src/mainboard/google/brya/variants/brya0/ramstage.c @@ -6,9 +6,9 @@ const struct cpu_power_limits limits[] = { /* SKU_ID, pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ /* All values are for baseline config as per bug:191906315 comment #10 */ - { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 3000, 15000, 39000, 39000, 100000}, - { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 4000, 28000, 43000, 43000, 105000}, - { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 5000, 45000, 80000, 80000, 159000}, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 3000, 15000, 39000, 39000, 100000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 4000, 28000, 43000, 43000, 105000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 5000, 45000, 80000, 80000, 159000 }, }; void variant_devtree_update(void) |