diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-07-27 12:17:51 -0600 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-07-28 20:02:53 +0000 |
| commit | 460fea65239db16efd4777b3d28f661b906ff469 (patch) | |
| tree | cf817715d7cad8cd40402dc41eea987b3d9f6495 /src/mainboard | |
| parent | 86b517f88edf1032cdc8f0b0df7ddad36151da50 (diff) | |
mb/google/brya/var/agah: Modify GPP_A8 programming
The EEs noticed this pin was misbehaving; it was accidentally set to a
low output, but should be open-drain (NC). This patch fixes that.
BUG=b:237837108
TEST=verified by EEs
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie76a951320c49b9fbc1f23b96f04c9f86ad44d42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/agah/gpio.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/agah/gpio.c b/src/mainboard/google/brya/variants/agah/gpio.c index 9afc607ad8..7eecd8b297 100644 --- a/src/mainboard/google/brya/variants/agah/gpio.c +++ b/src/mainboard/google/brya/variants/agah/gpio.c @@ -10,7 +10,7 @@ static const struct pad_config override_gpio_table[] = { /* A7 : SRCCLK_OE7# ==> LAN_WAKE_ODL */ PAD_CFG_GPI_SCI_LOW(GPP_A7, NONE, DEEP, EDGE_SINGLE), /* A8 : SRCCLKREQ7# ==> USB2_A2_RT_RST_ODL */ - PAD_CFG_GPO(GPP_A8, 1, DEEP), + PAD_NC(GPP_A8, NONE), /* A12 : SATAXPCIE1 ==> EN_PP3300_LAN_X */ PAD_CFG_GPO(GPP_A12, 1, DEEP), /* A14 : USB_OC1# ==> USB_C0_OC_ODL */ |