diff options
| author | Meera Ravindranath <meera.ravindranath@intel.com> | 2021-10-07 20:59:43 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-17 00:35:18 +0000 |
| commit | 3fd39467b559e954f4c83b060a0f824d9adc20c9 (patch) | |
| tree | aedbc8ac94eb74722bda6b35d85c5884555315f8 /src/mainboard | |
| parent | df99e57289ba2413cc82ef5f8dc70e37059eac31 (diff) | |
mb/intel/adlrvp: Fix S0ix regression
The following changes are needed to fix S0ix regression on RVP
1) Disable Clk src 3
2) Disable Ext FIVR settings
TEST=Boot adlrvp to OS, confirm S0ix is working.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b8b76b5527d8b80776cb7588ce6b12281af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree.cb | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index a00ad357d3..8926887c33 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -83,12 +83,6 @@ chip soc/intel/alderlake .clk_src = 0, }" - # Enable CPU PCIE RP 2 using CLK 3 - register "cpu_pcie_rp[CPU_RP(2)]" = "{ - .clk_req = 3, - .clk_src = 3, - }" - # Enable CPU PCIE RP 3 using CLK 4 register "cpu_pcie_rp[CPU_RP(3)]" = "{ .clk_req = 4, @@ -187,21 +181,6 @@ chip soc/intel/alderlake }, }" - # FIVR configurations - register "ext_fivr_settings" = "{ - .configure_ext_fivr = 1, - .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, - .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, - .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, - .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, - .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, - .v1p05_voltage_mv = 1050, - .vnn_voltage_mv = 1050, - .vnn_sx_voltage_mv = 1050, - .v1p05_icc_max_ma = 500, - .vnn_icc_max_ma = 500, - }" - device domain 0 on device ref pcie5 on end device ref igpu on end |