diff options
author | Varadarajan Narayanan <varada@codeaurora.org> | 2016-03-02 13:15:47 +0530 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2016-05-10 21:36:49 +0200 |
commit | 3bbd90173a9486b057aeb484ad5538b6e6cf42c7 (patch) | |
tree | 128ba6c8b2999294980b623a24870234bb77afa1 /src/mainboard | |
parent | dc17d2de346008aa648aab626dd2a8593b082685 (diff) |
google/gale: Initial commit for Gale board support
Copy 'storm' files as a template
BUG=chrome-os-partner:49249
TEST=None. Initial code. Not sure if it will even compile
BRANCH=none
Original-Commit-Id: 4bfabf22cb33ac2aacff0ebeed54655664505148
Original-Change-Id: I94e361911b89c5159b99f3d00efbcda94f763e71
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Signed-off-by: Kan Yan <kyan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/333177
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
squashed:
google/gale: Remove unwanted config option
2016.02 doesn't seem to like CONSOLE_CBMEM_DUMP_TO_UART
BUG=chrome-os-partner:49249
TEST=None. Initial code not sure if it will even compile
BRANCH=none
Original-Commit-Id: 44b91a8f83515936156206f9f273e0e5c62c3f17
Original-Change-Id: I9294ff602a05e4c9573fee3b9b51f9cc5305e192
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333302
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
google/gale: Update ipq806x/storm references
Since the files were taken from ipq806x/storm as
template. Update those references to reflect
ipq40xx/gale.
BUG=chrome-os-partner:49249
TEST=None. Initial code not sure if it will even compile
BRANCH=none
Original-Commit-Id: fa5962b757dbb6cc9e1e6d1e33e1e09ec6cb4cd2
Original-Change-Id: Ia330367a0547ac4306ef2514dc1305e2d65f80e4
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333292
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
google/gale: Update fill_lb_gpios for new scheme
This updates fill_lb_gpios to follow the new scheme introduced
in CL:337176.
BUG=none
BRANCH=none
TEST=chromeos.c compiles successfully for gale
Original-Commit-Id: 635d7fd71d91552bd7470faeb5637ba1a727f940
Original-Change-Id: I6f98325918b350645b9c19b71125bc12a54953ab
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/338651
google/gale: Add '.fmd' file
BUG=chrome-os-partner:49249
TEST=None. Initial code. Not sure if it will even compile
BRANCH=none
Original-Commit-Id: 474de31f7ed0adbe54251ca363e685019091b4e7
Original-Change-Id: I4019b110af676090e8751b315dadc5b601a56178
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333291
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Iad8e010371f3b9b92ab26eee4ba35c4f16d3732c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14642
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r-- | src/mainboard/google/gale/Kconfig | 63 | ||||
-rw-r--r-- | src/mainboard/google/gale/Kconfig.name | 2 | ||||
-rw-r--r-- | src/mainboard/google/gale/Makefile.inc | 43 | ||||
-rw-r--r-- | src/mainboard/google/gale/board_info.txt | 6 | ||||
-rw-r--r-- | src/mainboard/google/gale/boardid.c | 57 | ||||
-rw-r--r-- | src/mainboard/google/gale/bootblock.c | 61 | ||||
-rw-r--r-- | src/mainboard/google/gale/cdp.c | 72 | ||||
-rw-r--r-- | src/mainboard/google/gale/chromeos.c | 154 | ||||
-rw-r--r-- | src/mainboard/google/gale/chromeos.fmd | 33 | ||||
-rw-r--r-- | src/mainboard/google/gale/devicetree.cb | 18 | ||||
-rw-r--r-- | src/mainboard/google/gale/gsbi.c | 64 | ||||
-rw-r--r-- | src/mainboard/google/gale/mainboard.c | 131 | ||||
-rw-r--r-- | src/mainboard/google/gale/memlayout.ld | 14 | ||||
-rw-r--r-- | src/mainboard/google/gale/mmu.c | 68 | ||||
-rw-r--r-- | src/mainboard/google/gale/mmu.h | 24 | ||||
-rw-r--r-- | src/mainboard/google/gale/reset.c | 48 | ||||
-rw-r--r-- | src/mainboard/google/gale/romstage.c | 33 |
17 files changed, 891 insertions, 0 deletions
diff --git a/src/mainboard/google/gale/Kconfig b/src/mainboard/google/gale/Kconfig new file mode 100644 index 0000000000..0288c6e0e1 --- /dev/null +++ b/src/mainboard/google/gale/Kconfig @@ -0,0 +1,63 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_GOOGLE_GALE + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_QC_IPQ40XX + select BOARD_ID_AUTO + select BOARD_ROMSIZE_KB_8192 + select COMMON_CBFS_SPI_WRAPPER + select DRIVERS_I2C_WW_RING + select HAVE_HARD_RESET + select MAINBOARD_HAS_CHROMEOS + select SPI_FLASH + select SPI_FLASH_SPANSION + select SPI_FLASH_STMICRO + select DRIVERS_UART + +config CHROMEOS + select VBOOT_DISABLE_DEV_ON_RECOVERY + select VIRTUAL_DEV_SWITCH + select WIPEOUT_SUPPORTED + +config BOARD_VARIANT_DK01 + bool "pick this to build an image for DK01" + default n + +config MAINBOARD_DIR + string + default google/gale + +config MAINBOARD_PART_NUMBER + string + default "DK01" if BOARD_VARIANT_DK01 + default "Gale" + +config DRAM_SIZE_MB + int + default 512 if BOARD_VARIANT_DK01 + default 512 + +config DRIVER_TPM_I2C_BUS + hex + default 0x1 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x20 + +endif # BOARD_GOOGLE_GALE diff --git a/src/mainboard/google/gale/Kconfig.name b/src/mainboard/google/gale/Kconfig.name new file mode 100644 index 0000000000..e6c79ce665 --- /dev/null +++ b/src/mainboard/google/gale/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GOOGLE_GALE + bool "Gale" diff --git a/src/mainboard/google/gale/Makefile.inc b/src/mainboard/google/gale/Makefile.inc new file mode 100644 index 0000000000..491b5b5075 --- /dev/null +++ b/src/mainboard/google/gale/Makefile.inc @@ -0,0 +1,43 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += bootblock.c +bootblock-y += cdp.c +bootblock-y += mmu.c +bootblock-y += reset.c + +verstage-y += boardid.c +verstage-y += cdp.c +verstage-y += chromeos.c +verstage-y += gsbi.c +verstage-y += memlayout.ld +verstage-y += reset.c + +romstage-y += romstage.c +romstage-y += cdp.c +romstage-y += chromeos.c +romstage-y += mmu.c +romstage-y += reset.c + +ramstage-y += boardid.c +ramstage-y += cdp.c +ramstage-y += chromeos.c +ramstage-y += mainboard.c +ramstage-y += mmu.c +ramstage-y += reset.c + +bootblock-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld diff --git a/src/mainboard/google/gale/board_info.txt b/src/mainboard/google/gale/board_info.txt new file mode 100644 index 0000000000..c263c515b0 --- /dev/null +++ b/src/mainboard/google/gale/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Gale +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/gale/boardid.c b/src/mainboard/google/gale/boardid.c new file mode 100644 index 0000000000..295550fe2b --- /dev/null +++ b/src/mainboard/google/gale/boardid.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <gpio.h> +#include <console/console.h> +#include <stdlib.h> + +/* + * Storm boards dedicate to the board ID three GPIOs in tertiary mode: 29, 30 + * and 68. On proto0 GPIO68 is used and tied low, so it reads as 'zero' by + * gpio_base3_value(), whereas the other two pins are not connected + * and read as 'two'. This results in gpio_base3_value() returning + * 8 on proto0. + * + * Three tertitiary signals could represent 27 different values. To make + * calculated board ID value continuous and starting at zero, offset the + * calculated value by 19 (i.e. 27 - 8) and return modulo 27 of the offset + * number. This results in proto0 returning zero as the board ID, the future + * revisions will have the inputs configured to match the actual board + * revision. + */ + +static int board_id_value = -1; + +static uint8_t get_board_id(void) +{ + uint8_t bid; + gpio_t hw_rev_gpios[] = {[2] = 68, [1] = 30, [0] = 29}; /* 29 is LSB */ + int offset = 19; + + bid = gpio_base3_value(hw_rev_gpios, ARRAY_SIZE(hw_rev_gpios)); + bid = (bid + offset) % 27; + printk(BIOS_INFO, "Board ID %d\n", bid); + + return bid; +} + +uint8_t board_id(void) +{ + if (board_id_value < 0) + board_id_value = get_board_id(); + + return board_id_value; +} diff --git a/src/mainboard/google/gale/bootblock.c b/src/mainboard/google/gale/bootblock.c new file mode 100644 index 0000000000..8313501eff --- /dev/null +++ b/src/mainboard/google/gale/bootblock.c @@ -0,0 +1,61 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <console/console.h> +#include <symbols.h> + +#include "mmu.h" +#include <soc/usbl_if.h> + +static void dump_usbl_report(int section, sbl_ro_info *info) +{ + int i, num_log_entries; + + num_log_entries = info->num_log_entries; + if (!num_log_entries) + return; + + printk(BIOS_INFO, " Section %d log:\n", section); + for (i = 0; i < num_log_entries; i++) + printk(BIOS_INFO, " %-5d:%2.2x:%.*s\n", + info->log[i].time_stamp, + info->log[i].type, + sizeof(info->log[i].msg), + info->log[i].msg); +} + +void bootblock_mainboard_init(void) +{ + int i; + + setup_mmu(DRAM_NOT_INITIALIZED); + + if (((uintptr_t)maskrom_param < (uintptr_t)&_sram) || + ((uintptr_t)maskrom_param > (uintptr_t)&_esram)) { + printk(BIOS_INFO, "No uber-sbl parameter detected\n"); + return; + } + + /* Is maskrom parameter address set to a sensible value? */ + if ((maskrom_param->start_magic != UBER_SBL_SHARED_INFO_START_MAGIC) || + (maskrom_param->end_magic != UBER_SBL_SHARED_INFO_END_MAGIC)) { + + printk(BIOS_INFO, "Uber-sbl: invalid magic!\n"); + } else { + printk(BIOS_INFO, "Uber-sbl version: %s\n", + maskrom_param->version); + + for (i = 0; i < maskrom_param->num; i++) + dump_usbl_report(i, &maskrom_param->info[i]); + } +} diff --git a/src/mainboard/google/gale/cdp.c b/src/mainboard/google/gale/cdp.c new file mode 100644 index 0000000000..f8af96a88b --- /dev/null +++ b/src/mainboard/google/gale/cdp.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <gpio.h> +#include <soc/cdp.h> +#include <soc/ebi2.h> +#include <soc/clock.h> +#include <types.h> +#include <boardid.h> + +void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count) +{ + int i; + + for (i = 0; i < count; i++) { + gpio_tlmm_config(gpio->gpio, gpio->func, gpio->dir, + gpio->pull, gpio->drvstr, gpio->enable); + gpio++; + } +} + +static void configure_nand_gpio(void) +{ + /* EBI2 CS, CLE, ALE, WE, OE */ + gpio_tlmm_config(34, 1, 0, GPIO_NO_PULL, GPIO_10MA, GPIO_DISABLE); + gpio_tlmm_config(35, 1, 0, GPIO_NO_PULL, GPIO_10MA, GPIO_DISABLE); + gpio_tlmm_config(36, 1, 0, GPIO_NO_PULL, GPIO_10MA, GPIO_DISABLE); + gpio_tlmm_config(37, 1, 0, GPIO_NO_PULL, GPIO_10MA, GPIO_DISABLE); + gpio_tlmm_config(38, 1, 0, GPIO_NO_PULL, GPIO_10MA, GPIO_DISABLE); + + /* EBI2 BUSY */ + gpio_tlmm_config(39, 1, 0, GPIO_PULL_UP, GPIO_10MA, GPIO_DISABLE); + + /* EBI2 D7 - D0 */ + gpio_tlmm_config(40, 1, 0, GPIO_KEEPER, GPIO_10MA, GPIO_DISABLE); + gpio_tlmm_config(41, 1, 0, GPIO_KEEPER, GPIO_10MA, GPIO_DISABLE); + gpio_tlmm_config(42, 1, 0, GPIO_KEEPER, GPIO_10MA, GPIO_DISABLE); + gpio_tlmm_config(43, 1, 0, GPIO_KEEPER, GPIO_10MA, GPIO_DISABLE); + gpio_tlmm_config(44, 1, 0, GPIO_KEEPER, GPIO_10MA, GPIO_DISABLE); + gpio_tlmm_config(45, 1, 0, GPIO_KEEPER, GPIO_10MA, GPIO_DISABLE); + gpio_tlmm_config(46, 1, 0, GPIO_KEEPER, GPIO_10MA, GPIO_DISABLE); + gpio_tlmm_config(47, 1, 0, GPIO_KEEPER, GPIO_10MA, GPIO_DISABLE); +} + +void board_nand_init(void) +{ + struct ebi2cr_regs *ebi2_regs; + + if (board_id() != BOARD_ID_PROTO_0_2_NAND) + return; + + ebi2_regs = (struct ebi2cr_regs *) EBI2CR_BASE; + + nand_clock_config(); + configure_nand_gpio(); + + /* NAND Flash is connected to CS0 */ + clrsetbits_le32(&ebi2_regs->chip_select_cfg0, CS0_CFG_MASK, + CS0_CFG_SERIAL_FLASH_DEVICE); +} diff --git a/src/mainboard/google/gale/chromeos.c b/src/mainboard/google/gale/chromeos.c new file mode 100644 index 0000000000..a379280ca5 --- /dev/null +++ b/src/mainboard/google/gale/chromeos.c @@ -0,0 +1,154 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <boot/coreboot_tables.h> +#include <console/console.h> +#include <delay.h> +#include <drivers/i2c/ww_ring/ww_ring.h> +#include <gpio.h> +#include <soc/cdp.h> +#include <soc/gsbi.h> +#include <string.h> +#include <timer.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#define DEV_SW 15 +#define DEV_POL ACTIVE_LOW +#define REC_SW 16 +#define REC_POL ACTIVE_LOW +#define WP_SW 17 +#define WP_POL ACTIVE_LOW + +static int read_gpio(gpio_t gpio_num) +{ + gpio_tlmm_config_set(gpio_num, GPIO_FUNC_DISABLE, + GPIO_NO_PULL, GPIO_2MA, GPIO_DISABLE); + udelay(10); /* Should be enough to settle. */ + return gpio_get(gpio_num); +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {DEV_SW, ACTIVE_LOW, read_gpio(DEV_SW), "developer"}, + {REC_SW, ACTIVE_LOW, read_gpio(REC_SW), "recovery"}, + {WP_SW, ACTIVE_LOW, read_gpio(WP_SW), "write protect"}, + {-1, ACTIVE_LOW, 1, "power"}, + {-1, ACTIVE_LOW, 0, "lid"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_developer_mode_switch(void) +{ + return 0; +} + +/* + * The recovery switch on storm is overloaded: it needs to be pressed for a + * certain duration at startup to signal different requests: + * + * - keeping it pressed for 8 to 16 seconds after startup signals the need for + * factory reset (wipeout); + * - keeping it pressed for longer than 16 seconds signals the need for Chrome + * OS recovery. + * + * The state is read once and cached for following inquiries. The below enum + * lists possible states. + */ +enum switch_state { + not_probed = -1, + no_req, + recovery_req, + wipeout_req +}; + +static void display_pattern(int pattern) +{ + if (board_id() == BOARD_ID_WHIRLWIND_SP5) + ww_ring_display_pattern(GSBI_ID_7, pattern); +} + +#define WIPEOUT_MODE_DELAY_MS (8 * 1000) +#define RECOVERY_MODE_EXTRA_DELAY_MS (8 * 1000) + +static enum switch_state get_switch_state(void) +{ + struct stopwatch sw; + int sampled_value; + static enum switch_state saved_state = not_probed; + + if (saved_state != not_probed) + return saved_state; + + sampled_value = read_gpio(REC_SW) ^ !REC_POL; + + if (!sampled_value) { + saved_state = no_req; + display_pattern(WWR_NORMAL_BOOT); + return saved_state; + } + + display_pattern(WWR_RECOVERY_PUSHED); + printk(BIOS_INFO, "recovery button pressed\n"); + + stopwatch_init_msecs_expire(&sw, WIPEOUT_MODE_DELAY_MS); + + do { + sampled_value = read_gpio(REC_SW) ^ !REC_POL; + if (!sampled_value) + break; + } while (!stopwatch_expired(&sw)); + + if (sampled_value) { + display_pattern(WWR_WIPEOUT_REQUEST); + printk(BIOS_INFO, "wipeout requested, checking recovery\n"); + stopwatch_init_msecs_expire(&sw, RECOVERY_MODE_EXTRA_DELAY_MS); + do { + sampled_value = read_gpio(REC_SW) ^ !REC_POL; + if (!sampled_value) + break; + } while (!stopwatch_expired(&sw)); + + if (sampled_value) { + saved_state = recovery_req; + display_pattern(WWR_RECOVERY_REQUEST); + printk(BIOS_INFO, "recovery requested\n"); + } else { + saved_state = wipeout_req; + } + } else { + saved_state = no_req; + display_pattern(WWR_NORMAL_BOOT); + } + + return saved_state; +} + +int get_recovery_mode_switch(void) +{ + return get_switch_state() == recovery_req; +} + +int get_wipeout_mode_switch(void) +{ + return get_switch_state() == wipeout_req; +} + +int get_write_protect_state(void) +{ + return read_gpio(WP_SW) ^ !WP_POL; +} diff --git a/src/mainboard/google/gale/chromeos.fmd b/src/mainboard/google/gale/chromeos.fmd new file mode 100644 index 0000000000..a7b40593b6 --- /dev/null +++ b/src/mainboard/google/gale/chromeos.fmd @@ -0,0 +1,33 @@ +FLASH@0x0 0x800000 { + WP_RO@0x0 0x400000 { + RO_SECTION@0x0 0x3e0000 { + BOOTBLOCK@0 128K + COREBOOT(CBFS)@0x20000 0x2e0000 + FMAP@0x300000 0x1000 + GBB@0x301000 0xdef00 + RO_FRID@0x3dff00 0x100 + } + RO_VPD@0x3e0000 0x20000 + } + RW_SECTION_A@0x400000 0x160000 { + VBLOCK_A@0x0 0x2000 + FW_MAIN_A(CBFS)@0x2000 0x14df00 + RW_FWID_A@0x14ff00 0x100 + RW_SHARED@0x150000 0x10000 { + SHARED_DATA@0x0 0x10000 + } + } + RW_GPT@0x560000 0x20000 { + RW_GPT_PRIMARY@0x0 0x10000 + RW_GPT_SECONDARY@0x10000 0x10000 + } + RW_SECTION_B@0x580000 0x160000 { + VBLOCK_B@0x0 0x2000 + FW_MAIN_B(CBFS)@0x2000 0x14df00 + RW_FWID_B@0x14ff00 0x100 + } + RW_VPD@0x6e0000 0x8000 + RW_ELOG@0x6e8000 0x8000 + RW_NVRAM@0x6f0000 0x10000 + RW_LEGACY@0x700000 0x100000 +} diff --git a/src/mainboard/google/gale/devicetree.cb b/src/mainboard/google/gale/devicetree.cb new file mode 100644 index 0000000000..f34a309caf --- /dev/null +++ b/src/mainboard/google/gale/devicetree.cb @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/qualcomm/ipq40xx + device cpu_cluster 0 on end +end diff --git a/src/mainboard/google/gale/gsbi.c b/src/mainboard/google/gale/gsbi.c new file mode 100644 index 0000000000..915f317df9 --- /dev/null +++ b/src/mainboard/google/gale/gsbi.c @@ -0,0 +1,64 @@ +/* + * This file is part of the depthcharge project. + * + * Copyright (C) 2014 - 2015 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <soc/gpio.h> +#include <soc/gsbi.h> +#include <soc/qup.h> + +#define GPIO_FUNC_I2C 0x1 + +int gsbi_init_board(gsbi_id_t gsbi_id) +{ + switch (gsbi_id) { + case GSBI_ID_7: + gpio_tlmm_config_set(8, GPIO_FUNC_I2C, + GPIO_NO_PULL, GPIO_2MA, 1); + gpio_tlmm_config_set(9, GPIO_FUNC_I2C, + GPIO_NO_PULL, GPIO_2MA, 1); + break; + case GSBI_ID_4: + /* Configure GPIOs 13 - SCL, 12 - SDA, 2mA gpio_en */ + gpio_tlmm_config_set(12, GPIO_FUNC_I2C, + GPIO_NO_PULL, GPIO_2MA, 1); + gpio_tlmm_config_set(13, GPIO_FUNC_I2C, + GPIO_NO_PULL, GPIO_2MA, 1); + break; + case GSBI_ID_1: + /* Configure GPIOs 54 - SCL, 53 - SDA, 2mA gpio_en */ + gpio_tlmm_config_set(54, GPIO_FUNC_I2C, + GPIO_NO_PULL, GPIO_2MA, 1); + gpio_tlmm_config_set(53, GPIO_FUNC_I2C, + GPIO_NO_PULL, GPIO_2MA, 1); + break; + default: + return 1; + } + + return 0; +} diff --git a/src/mainboard/google/gale/mainboard.c b/src/mainboard/google/gale/mainboard.c new file mode 100644 index 0000000000..73c288b80e --- /dev/null +++ b/src/mainboard/google/gale/mainboard.c @@ -0,0 +1,131 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <boot/coreboot_tables.h> +#include <delay.h> +#include <device/device.h> +#include <gpio.h> +#include <soc/clock.h> +#include <soc/soc_services.h> +#include <soc/usb.h> +#include <symbols.h> + +#include <vendorcode/google/chromeos/chromeos.h> +#include "mmu.h" + +#define USB_ENABLE_GPIO 51 + +static void setup_usb(void) +{ +#if !CONFIG_BOARD_VARIANT_AP148 + gpio_tlmm_config_set(USB_ENABLE_GPIO, FUNC_SEL_GPIO, + GPIO_PULL_UP, GPIO_10MA, GPIO_ENABLE); + gpio_set(USB_ENABLE_GPIO, 1); +#endif + usb_clock_config(); + + setup_usb_host1(); +} + +#define TPM_RESET_GPIO 22 +static void setup_tpm(void) +{ + if (board_id() != BOARD_ID_PROTO_0) + return; /* Only proto0 have TPM reset connected to GPIO22 */ + + gpio_tlmm_config_set(TPM_RESET_GPIO, FUNC_SEL_GPIO, GPIO_PULL_UP, + GPIO_4MA, GPIO_ENABLE); + /* + * Generate a reset pulse. The spec calls for 80 us minimum, let's + * make it twice as long. If the output was driven low originally, the + * reset pulse will be even longer. + */ + gpio_set(TPM_RESET_GPIO, 0); + udelay(160); + gpio_set(TPM_RESET_GPIO, 1); +} + +#define SW_RESET_GPIO 26 +static void assert_sw_reset(void) +{ + if (board_id() == BOARD_ID_PROTO_0) + return; + + /* + * only proto0.2 and later care about this. We want to keep the + * ethernet switch in reset, otherwise it comes up in default + * (bridging) mode. + */ + gpio_tlmm_config_set(SW_RESET_GPIO, FUNC_SEL_GPIO, + GPIO_PULL_UP, GPIO_4MA, GPIO_ENABLE); + + gpio_set(SW_RESET_GPIO, 1); +} + +static void mainboard_init(device_t dev) +{ + /* disable mmu and d-cache before setting up secure world.*/ + dcache_mmu_disable(); + start_tzbsp(); + /* Setup mmu and d-cache again as non secure entries. */ + setup_mmu(DRAM_INITIALIZED); + start_rpm(); + setup_usb(); + assert_sw_reset(); + setup_tpm(); + /* Functionally a 0-cost no-op if NAND is not present */ + board_nand_init(); + +#if IS_ENABLED(CONFIG_CHROMEOS) + /* Copy WIFI calibration data into CBMEM. */ + cbmem_add_vpd_calibration_data(); +#endif + + /* + * Make sure bootloader can issue sounds The frequency is calculated + * as "<frame_rate> * <bit_width> * <channels> * 4", i.e. + * + * 48000 * 2 * 16 * 4 = 6144000 + */ + audio_clock_config(6144000); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = "gale", + .enable_dev = mainboard_enable, +}; + +void lb_board(struct lb_header *header) +{ + struct lb_range *dma; + + dma = (struct lb_range *)lb_new_record(header); + dma->tag = LB_TAB_DMA; + dma->size = sizeof(*dma); + dma->range_start = (uintptr_t)_dma_coherent; + dma->range_size = _dma_coherent_size; + +#if IS_ENABLED(CONFIG_CHROMEOS) + /* Retrieve the switch interface MAC addressses. */ + lb_table_add_macs_from_vpd(header); +#endif +} diff --git a/src/mainboard/google/gale/memlayout.ld b/src/mainboard/google/gale/memlayout.ld new file mode 100644 index 0000000000..2c3330651d --- /dev/null +++ b/src/mainboard/google/gale/memlayout.ld @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/memlayout.ld> diff --git a/src/mainboard/google/gale/mmu.c b/src/mainboard/google/gale/mmu.c new file mode 100644 index 0000000000..4d2e9a0123 --- /dev/null +++ b/src/mainboard/google/gale/mmu.c @@ -0,0 +1,68 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cache.h> +#include <symbols.h> +#include "mmu.h" + +/* convenient shorthand (in MB) */ +#define RPM_START ((uintptr_t)_rpm / KiB) +#define RPM_END ((uintptr_t)_erpm / KiB) +#define RPM_SIZE (RPM_END - RPM_START) +#define SRAM_START ((uintptr_t)_sram / KiB) +#define SRAM_END ((uintptr_t)_esram / KiB) +#define DRAM_START ((uintptr_t)_dram / MiB) +#define DRAM_SIZE (CONFIG_DRAM_SIZE_MB) +#define DRAM_END (DRAM_START + DRAM_SIZE) + +/* DMA memory for drivers */ +#define DMA_START ((uintptr_t)_dma_coherent / MiB) +#define DMA_SIZE (_dma_coherent_size / MiB) + +void setup_dram_mappings(enum dram_state dram) +{ + if (dram == DRAM_INITIALIZED) { + mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); + /* Map DMA memory */ + mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF); + } else { + mmu_disable_range(DRAM_START, DRAM_SIZE); + /* Map DMA memory */ + mmu_disable_range(DMA_START, DMA_SIZE); + } +} + +void setup_mmu(enum dram_state dram) +{ + dcache_mmu_disable(); + + /* start with mapping everything as strongly ordered. */ + mmu_config_range(0, 4096, DCACHE_OFF); + + /* Map Device memory. */ + mmu_config_range_kb(RPM_START, RPM_SIZE, DCACHE_OFF); + + mmu_config_range_kb(SRAM_START, SRAM_END - SRAM_START, + DCACHE_WRITEBACK); + + /* Map DRAM memory */ + setup_dram_mappings(dram); + + mmu_disable_range(DRAM_END, 4096 - DRAM_END); + + /* disable Page 0 for trapping NULL pointer references. */ + mmu_disable_range_kb(0, 1); + + mmu_init(); + + dcache_mmu_enable(); +} diff --git a/src/mainboard/google/gale/mmu.h b/src/mainboard/google/gale/mmu.h new file mode 100644 index 0000000000..956553d2c3 --- /dev/null +++ b/src/mainboard/google/gale/mmu.h @@ -0,0 +1,24 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> + +extern u8 _rpm[]; +extern u8 _erpm[]; + +enum dram_state { + DRAM_INITIALIZED = 0, + DRAM_NOT_INITIALIZED = 1, +}; + +void setup_dram_mappings(enum dram_state dram); +void setup_mmu(enum dram_state); diff --git a/src/mainboard/google/gale/reset.c b/src/mainboard/google/gale/reset.c new file mode 100644 index 0000000000..94dcd4befd --- /dev/null +++ b/src/mainboard/google/gale/reset.c @@ -0,0 +1,48 @@ +/* + * + * This file is part of the coreboot project. + * + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <soc/iomap.h> +#include <reset.h> + +/* Watchdog bite time set to default reset value */ +#define RESET_WDT_BITE_TIME 0x31F3 + +/* Watchdog bark time value is kept larger than the watchdog timeout + * of 0x31F3, effectively disabling the watchdog bark interrupt + */ +#define RESET_WDT_BARK_TIME (5 * RESET_WDT_BITE_TIME) + +static void wdog_reset(void) +{ + printk(BIOS_DEBUG, "\nResetting with watchdog!\n"); + + write32(APCS_WDT0_EN, 0); + write32(APCS_WDT0_RST, 1); + write32(APCS_WDT0_BARK_TIME, RESET_WDT_BARK_TIME); + write32(APCS_WDT0_BITE_TIME, RESET_WDT_BITE_TIME); + write32(APCS_WDT0_EN, 1); + write32(APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE, 1); + + for (;;) + ; +} + +void hard_reset(void) +{ + wdog_reset(); +} diff --git a/src/mainboard/google/gale/romstage.c b/src/mainboard/google/gale/romstage.c new file mode 100644 index 0000000000..c1b86541fb --- /dev/null +++ b/src/mainboard/google/gale/romstage.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> +#include <console/console.h> +#include <program_loading.h> +#include <soc/soc_services.h> +#include "mmu.h" + +void main(void) +{ + console_init(); + initialize_dram(); + + /* Add dram mappings to mmu tables. */ + setup_dram_mappings(DRAM_INITIALIZED); + + cbmem_initialize_empty(); + run_ramstage(); +} |