diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-07-12 09:55:32 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-14 12:42:51 +0000 |
| commit | 35c61216f47338b4b20907f797662447c89f42bb (patch) | |
| tree | 0c3e077bb646708080e0f923f508cfd0248a4c5e /src/mainboard | |
| parent | 9ffaf7f69260b2d08a01cbe155b58cfc932eea6a (diff) | |
mb/google/rex: Add chip config for USB devices
+-------------+----------------+------------+
| USB 2.0 | Connector Type | OC Mapping |
+-------------+----------------+------------+
| 1 | NC | NC |
+-------------+----------------+------------+
| 2 | Type-C | OC_0 |
+-------------+----------------+------------+
| 3 | NC | NC |
+-------------+----------------+------------+
| 4 | Type-C | NA |
+-------------+----------------+------------+
| 5 | WWAN | NA |
+-------------+----------------+------------+
| 6 | Camera | NA |
+-------------+----------------+------------+
| 7 | NC | NC |
+-------------+----------------+------------+
| 8 | DCI | NA |
+-------------+----------------+------------+
| 9 | Type-A | OC_3 |
+-------------+----------------+------------+
| 10 | BT | NA |
+-------------+----------------+------------+
+---------------------+-------------------+------------+
| USB 3.2 Gen 2x1 | Connector Details | OC Mapping |
+---------------------+-------------------+------------+
| 1 | Type-A | OC_3 |
+---------------------+-------------------+------------+
| 2 | DCI | NA |
+---------------------+-------------------+------------+
+------+-------------------+------------+
| TCPx | Connector Details | OC Mapping |
+------+-------------------+------------+
| 1 | Type C port 0 | OC_0 |
+------+-------------------+------------+
| 3 | Type C port 1 | NA |
+------+-------------------+------------+
BUG=b:224325352
TEST=Able to build Google/Rex and boot to emulator.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iecab1318f683e3b53441cafe909bcfd978ee126b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/rex/variants/rex0/overridetree.cb | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index e0cbc6e7d3..65c1c81671 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -1,5 +1,18 @@ chip soc/intel/meteorlake + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A0 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # DCI + + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)" + register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + register "serial_io_gspi_mode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, [PchSerialIoIndexGSPI1] = PchSerialIoPci, |