diff options
| author | Wentao Qin <qinwentao@huaqin.corp-partner.google.com> | 2023-05-29 18:47:00 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-05-31 18:49:54 +0000 |
| commit | 23c40997b408ba94328fdf7b8f1c4325512f15d7 (patch) | |
| tree | fae50972be7c7ec9b298225ed41fd21a7560d685 /src/mainboard | |
| parent | aebbaa6c331f2eaf9df34e77d839d818a1dfc1c9 (diff) | |
mb/google/rex/var/screebo: Set TCC to 90°C
Set tcc_offset value to 20 in devicetree for Thermal Control Circuit
(TCC) activation feature for proto phase.
BUG=b:282865187
BRANCH=None
TEST=Build FW and test on Screebo board
Change-Id: I3a929aa20a700376d2a0a150911fed34e67f78eb
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75360
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/rex/variants/screebo/overridetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index 1178c07b68..ec59b8ff64 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -50,6 +50,9 @@ chip soc/intel/meteorlake [PchSerialIoIndexI2C5] = PchSerialIoPci, }" + # Temporary setting TCC of 90C = Tj max - Tcc + register "tcc_offset" = "20" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | |