AGESA boards: Add prepare_for_resume()

Use one common implementation for all AGESA platforms.

Change-Id: I410f8e0a9c75445882d67659cde00004eb7ad6b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6084
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

11 files changed, 11 insertions, 269 deletions

diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index 8d2156e507..dc52d16688 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -41,9 +41,6 @@
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
-#if CONFIG_HAVE_ACPI_RESUME
-	void *resume_backup_memory;
-#endif
 
 	/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
 	 *  LpcClk[1:0]".  To be consistent with Parmer, setting to 4mA
@@ -133,27 +130,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 			printk(BIOS_DEBUG, "passed.\n");
 
 		post_code(0x61);
-		printk(BIOS_DEBUG, "Find resume memory location\n");
-		resume_backup_memory = (void *)backup_resume();
-
-		post_code(0x62);
-		printk(BIOS_DEBUG, "Move CAR stack.\n");
-		move_stack_high_mem();
-		printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
-		post_code(0x63);
-		disable_cache_as_ram();
-		printk(BIOS_DEBUG, "CAR disabled.\n");
-		set_resume_cache();
-
-		/*
-		 * Copy the system memory that is in the ramstage area to the
-		 * reserved area.
-		 */
-		if (resume_backup_memory)
-			memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
-		printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+		prepare_for_resume();
 	}
 #endif
 
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c
index 36a6b8a175..8c0afa5801 100644
--- a/src/mainboard/amd/parmer/romstage.c
+++ b/src/mainboard/amd/parmer/romstage.c
@@ -41,9 +41,6 @@
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
-#if CONFIG_HAVE_ACPI_RESUME
-	void *resume_backup_memory;
-#endif
 	val = agesawrapper_amdinitmmio();
 
 	hudson_lpc_port80();
@@ -116,27 +113,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 			printk(BIOS_DEBUG, "passed.\n");
 
 		post_code(0x61);
-		printk(BIOS_DEBUG, "Find resume memory location\n");
-		resume_backup_memory = (void *)backup_resume();
-
-		post_code(0x62);
-		printk(BIOS_DEBUG, "Move CAR stack.\n");
-		move_stack_high_mem();
-		printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
-		post_code(0x63);
-		disable_cache_as_ram();
-		printk(BIOS_DEBUG, "CAR disabled.\n");
-		set_resume_cache();
-
-		/*
-		 * Copy the system memory that is in the ramstage area to the
-		 * reserved area.
-		 */
-		if (resume_backup_memory)
-			memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
-		printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+		prepare_for_resume();
 	}
 #endif
 
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 5908421545..32b85c3b8e 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -50,10 +50,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-#if CONFIG_HAVE_ACPI_RESUME
-	void *resume_backup_memory;
-#endif
-
 	/*
 	 * All cores: allow caching of flash chip code and data
 	 * (there are no cache-as-ram reliability concerns with family 14h)
@@ -145,27 +141,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 			printk(BIOS_DEBUG, "passed.\n");
 
 		post_code(0x61);
-		printk(BIOS_DEBUG, "Find resume memory location\n");
-		resume_backup_memory = backup_resume();
-
-		post_code(0x62);
-		printk(BIOS_DEBUG, "Move CAR stack.\n");
-		move_stack_high_mem();
-		printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
-		post_code(0x63);
-		disable_cache_as_ram();
-		printk(BIOS_DEBUG, "CAR disabled.\n");
-		set_resume_cache();
-
-		/*
-		 * Copy the system memory that is in the ramstage area to the
-		 * reserved area.
-		 */
-		if (resume_backup_memory)
-			memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
-		printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+		prepare_for_resume();
 	}
 #endif
 
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index 1461c4c786..063d2d9d86 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -46,9 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 val;
 	u8 byte;
 	device_t dev;
-#if CONFIG_HAVE_ACPI_RESUME
-	void *resume_backup_memory;
-#endif
 	val = agesawrapper_amdinitmmio();
 
 	hudson_lpc_port80();
@@ -133,27 +130,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 			printk(BIOS_DEBUG, "passed.\n");
 
 		post_code(0x61);
-		printk(BIOS_DEBUG, "Find resume memory location\n");
-		resume_backup_memory = (void *)backup_resume();
-
-		post_code(0x62);
-		printk(BIOS_DEBUG, "Move CAR stack.\n");
-		move_stack_high_mem();
-		printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
-		post_code(0x63);
-		disable_cache_as_ram();
-		printk(BIOS_DEBUG, "CAR disabled.\n");
-		set_resume_cache();
-
-		/*
-		 * Copy the system memory that is in the ramstage area to the
-		 * reserved area.
-		 */
-		if (resume_backup_memory)
-			memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
-		printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+		prepare_for_resume();
 	}
 #endif
 
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c
index 382ad5bb99..8ed5e05626 100644
--- a/src/mainboard/asrock/imb-a180/romstage.c
+++ b/src/mainboard/asrock/imb-a180/romstage.c
@@ -46,9 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val, t32;
 	u32 *addr32;
-#if CONFIG_HAVE_ACPI_RESUME
-	void *resume_backup_memory;
-#endif
 
 	/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
 	 *  LpcClk[1:0]".  To be consistent with Parmer, setting to 4mA
@@ -157,27 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 			printk(BIOS_DEBUG, "passed.\n");
 
 		post_code(0x61);
-		printk(BIOS_DEBUG, "Find resume memory location\n");
-		resume_backup_memory = (void *)backup_resume();
-
-		post_code(0x62);
-		printk(BIOS_DEBUG, "Move CAR stack.\n");
-		move_stack_high_mem();
-		printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
-		post_code(0x63);
-		disable_cache_as_ram();
-		printk(BIOS_DEBUG, "CAR disabled.\n");
-		set_resume_cache();
-
-		/*
-		 * Copy the system memory that is in the ramstage area to the
-		 * reserved area.
-		 */
-		if (resume_backup_memory)
-			memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
-		printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+		prepare_for_resume();
 	}
 #endif
 
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index 03f4bb1767..c8e102bfc7 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -75,9 +75,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	hudson_lpc_port80();
 #endif
 
-#if CONFIG_HAVE_ACPI_RESUME
-	void *resume_backup_memory;
-#endif
 	val = agesawrapper_amdinitmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
@@ -181,27 +178,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 			printk(BIOS_DEBUG, "passed.\n");
 
 		post_code(0x61);
-		printk(BIOS_DEBUG, "Find resume memory location\n");
-		resume_backup_memory = (void *)backup_resume();
-
-		post_code(0x62);
-		printk(BIOS_DEBUG, "Move CAR stack.\n");
-		move_stack_high_mem();
-		printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
-		post_code(0x63);
-		disable_cache_as_ram();
-		printk(BIOS_DEBUG, "CAR disabled.\n");
-		set_resume_cache();
-
-		/*
-		 * Copy the system memory that is in the ramstage area to the
-		 * reserved area.
-		 */
-		if (resume_backup_memory)
-			memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
-		printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+		prepare_for_resume();
 	}
 #endif
 
diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c
index 63a2be861e..c6119926a6 100755
--- a/src/mainboard/gizmosphere/gizmo/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo/romstage.c
@@ -51,10 +51,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 val;
 	msr_t msr;
 
-#if CONFIG_HAVE_ACPI_RESUME
-	void *resume_backup_memory;
-#endif
-
 	/*
 	 * All cores: allow caching of flash chip code and data
 	 * (there are no cache-as-ram reliability concerns with family 14h)
@@ -153,27 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 			printk(BIOS_DEBUG, "passed.\n");
 
 		post_code(0x61);
-		printk(BIOS_DEBUG, "Find resume memory location\n");
-		resume_backup_memory = backup_resume();
-
-		post_code(0x62);
-		printk(BIOS_DEBUG, "Move CAR stack.\n");
-		move_stack_high_mem();
-		printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
-		post_code(0x63);
-		disable_cache_as_ram();
-		printk(BIOS_DEBUG, "CAR disabled.\n");
-		set_resume_cache();
-
-		/*
-		 * Copy the system memory that is in the ramstage area to the
-		 * reserved area.
-		 */
-		if (resume_backup_memory)
-			memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
-		printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+		prepare_for_resume();
 	}
 #endif
 
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
index cb4268cc35..4b433c9f0b 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
@@ -38,9 +38,6 @@
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
-#if CONFIG_HAVE_ACPI_RESUME
-	void *resume_backup_memory;
-#endif
 	val = agesawrapper_amdinitmmio();
 
 	hudson_lpc_port80();
@@ -113,27 +110,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 			printk(BIOS_DEBUG, "passed.\n");
 
 		post_code(0x61);
-		printk(BIOS_DEBUG, "Find resume memory location\n");
-		resume_backup_memory = (void *)backup_resume();
-
-		post_code(0x62);
-		printk(BIOS_DEBUG, "Move CAR stack.\n");
-		move_stack_high_mem();
-		printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
-		post_code(0x63);
-		disable_cache_as_ram();
-		printk(BIOS_DEBUG, "CAR disabled.\n");
-		set_resume_cache();
-
-		/*
-		 * Copy the system memory that is in the ramstage area to the
-		 * reserved area.
-		 */
-		if (resume_backup_memory)
-			memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
-		printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+		prepare_for_resume();
 	}
 #endif
 
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index 25459d7d90..b49ea81a0c 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -66,10 +66,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-#if CONFIG_HAVE_ACPI_RESUME
-	void *resume_backup_memory;
-#endif
-
 	/*
 	 * All cores: allow caching of flash chip code and data
 	 * (there are no cache-as-ram reliability concerns with family 14h)
@@ -161,27 +157,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 			printk(BIOS_DEBUG, "passed.\n");
 
 		post_code(0x61);
-		printk(BIOS_DEBUG, "Find resume memory location\n");
-		resume_backup_memory = backup_resume();
-
-		post_code(0x62);
-		printk(BIOS_DEBUG, "Move CAR stack.\n");
-		move_stack_high_mem();
-		printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
-		post_code(0x63);
-		disable_cache_as_ram();
-		printk(BIOS_DEBUG, "CAR disabled.\n");
-		set_resume_cache();
-
-		/*
-		 * Copy the system memory that is in the ramstage area to the
-		 * reserved area.
-		 */
-		if (resume_backup_memory)
-			memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
-		printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+		prepare_for_resume();
 	}
 #endif /* CONFIG_HAVE_ACPI_RESUME */
 
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c
index 794588311e..06b365a0d2 100644
--- a/src/mainboard/lippert/frontrunner-af/romstage.c
+++ b/src/mainboard/lippert/frontrunner-af/romstage.c
@@ -49,10 +49,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-#if CONFIG_HAVE_ACPI_RESUME
-	void *resume_backup_memory;
-#endif
-
 	/*
 	 * All cores: allow caching of flash chip code and data
 	 * (there are no cache-as-ram reliability concerns with family 14h)
@@ -148,27 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 			printk(BIOS_DEBUG, "passed.\n");
 
 		post_code(0x61);
-		printk(BIOS_DEBUG, "Find resume memory location\n");
-		resume_backup_memory = backup_resume();
-
-		post_code(0x62);
-		printk(BIOS_DEBUG, "Move CAR stack.\n");
-		move_stack_high_mem();
-		printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
-		post_code(0x63);
-		disable_cache_as_ram();
-		printk(BIOS_DEBUG, "CAR disabled.\n");
-		set_resume_cache();
-
-		/*
-		 * Copy the system memory that is in the ramstage area to the
-		 * reserved area.
-		 */
-		if (resume_backup_memory)
-			memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
-		printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+		prepare_for_resume();
 	}
 #endif
 
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index b8bd744522..6a5c580dcb 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -50,10 +50,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-#if CONFIG_HAVE_ACPI_RESUME
-	void *resume_backup_memory;
-#endif
-
 	/*
 	 * All cores: allow caching of flash chip code and data
 	 * (there are no cache-as-ram reliability concerns with family 14h)
@@ -149,27 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 			printk(BIOS_DEBUG, "passed.\n");
 
 		post_code(0x61);
-		printk(BIOS_DEBUG, "Find resume memory location\n");
-		resume_backup_memory = backup_resume();
-
-		post_code(0x62);
-		printk(BIOS_DEBUG, "Move CAR stack.\n");
-		move_stack_high_mem();
-		printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
-		post_code(0x63);
-		disable_cache_as_ram();
-		printk(BIOS_DEBUG, "CAR disabled.\n");
-		set_resume_cache();
-
-		/*
-		 * Copy the system memory that is in the ramstage area to the
-		 * reserved area.
-		 */
-		if (resume_backup_memory)
-			memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
-		printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+		prepare_for_resume();
 	}
 #endif