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authorYidi Lin <yidi.lin@mediatek.com>2015-12-28 16:14:42 +0800
committerPatrick Georgi <pgeorgi@google.com>2016-03-12 09:07:21 +0100
commit22d94ba8a2178b587660f75b221ec06dec776c34 (patch)
tree8ca16ae5fa0f1d4c6d19c01d6e4c9fa5bce054a9 /src/mainboard
parente2979df3dfb80baa3cbfd41c50e34b74bc878845 (diff)
google/oak: Configure SPI_LEVEL_ENABLE pin for rev5
Oak introduces a 1.8V to 3.3V level shifter for EC SPI bus after rev5. BRANCH=none BUG=none TEST=emerge-oak coreboot Change-Id: I71868b003fc71dee0532033299afc155a9fbec9c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 030b478fedf046a7b818696779299c591415fcbd Original-Change-Id: Ibff9705832700867279cb1b39b752b8f5f27cf33 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/320026 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13970 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/oak/bootblock.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c
index 49cf5ddf65..2c13b14720 100644
--- a/src/mainboard/google/oak/bootblock.c
+++ b/src/mainboard/google/oak/bootblock.c
@@ -17,6 +17,7 @@
#include <boardid.h>
#include <bootblock_common.h>
#include <delay.h>
+#include <gpio.h>
#include <soc/gpio.h>
#include <soc/i2c.h>
#include <soc/mt6391.h>
@@ -79,6 +80,10 @@ void bootblock_mainboard_init(void)
/* set nor related GPIO */
nor_set_gpio_pinmux();
+ /* SPI_LEVEL_ENABLE: Enable 1.8V to 3.3V level shifter for EC SPI bus */
+ if (board_id() > 4)
+ gpio_output(PAD_SRCLKENAI2, 1);
+
/* Init i2c bus 2 Timing register for TPM */
mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS);