AGESA: Trace execution with AGESA_EVENTLOG()

Change-Id: I5601ed92ca808603b0a9edad118ca54aa168aceb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7604
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)

21 files changed, 129 insertions, 150 deletions

diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
index 3b13ee62ed..b1e9a61ec2 100644
--- a/src/mainboard/amd/dinar/romstage.c
+++ b/src/mainboard/amd/dinar/romstage.c
@@ -30,7 +30,6 @@
 #include <console/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include <superio/smsc/sch4037/sch4037.h>
 #include <superio/smsc/sio1036/sio1036.h>
@@ -64,7 +63,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	}
 
 	post_code(0x32);
-	AGESAWRAPPER(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	/* Halt if there was a built in self test failure */
 	post_code(0x33);
@@ -81,10 +80,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	}
 
 	post_code(0x35);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	post_code(0x36);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	post_code(0x37);
 	nb_Poweron_Init();
@@ -93,10 +92,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 
 	post_code(0x39);
-	AGESAWRAPPER(amdinitpost);
+	agesawrapper_amdinitpost();
 
 	post_code(0x40);
-	AGESAWRAPPER(amdinitenv);
+	agesawrapper_amdinitenv();
 
 
 	post_code(0x43);
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index e0cf1d3b05..3a5c761530 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -32,7 +32,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include <superio/smsc/kbc1100/kbc1100.h>
 #include "cpu/x86/lapic.h"
@@ -75,19 +74,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x35);
-	AGESAWRAPPER(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	post_code(0x39);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	post_code(0x40);
-	AGESAWRAPPER(amdinitpost);
+	agesawrapper_amdinitpost();
 
 	post_code(0x41);
-	AGESAWRAPPER(amdinitenv);
+	agesawrapper_amdinitenv();
 
 	post_code(0x50);
 	copy_and_run();
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index b1dcb5818a..abab68844a 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -31,7 +31,6 @@
 #include <console/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/lapic.h"
 #include "southbridge/amd/agesa/hudson/hudson.h"
@@ -51,7 +50,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	outb(0xD2, 0xcd6);
 	outb(0x00, 0xcd7);
 
-	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	/* Set LPC decode enables. */
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
@@ -81,29 +80,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		val = inb(0xcd6);
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 	post_code(0x38);
 	printk(BIOS_DEBUG, "Got past yangtze_early_setup\n");
 
 	post_code(0x39);
 
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 	int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
 	if (!s3resume) {
 		post_code(0x40);
-		AGESAWRAPPER(amdinitpost);
+		agesawrapper_amdinitpost();
 		post_code(0x41);
-		AGESAWRAPPER(amdinitenv);
+		agesawrapper_amdinitenv();
 		/* TODO: Disable cache is not ok. */
 		disable_cache_as_ram();
 	} else { /* S3 detect */
 		printk(BIOS_INFO, "S3 detected\n");
 
 		post_code(0x60);
-		AGESAWRAPPER(amdinitresume);
+		agesawrapper_amdinitresume();
 
 		agesawrapper_amdinitcpuio();
-		AGESAWRAPPER(amds3laterestore);
+		agesawrapper_amds3laterestore();
 
 		post_code(0x61);
 		prepare_for_resume();
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c
index fe84a90413..9a55e8060b 100644
--- a/src/mainboard/amd/parmer/romstage.c
+++ b/src/mainboard/amd/parmer/romstage.c
@@ -31,7 +31,6 @@
 #include <console/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/lapic.h"
 #include "southbridge/amd/agesa/hudson/hudson.h"
@@ -43,7 +42,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	/* Set LPC decode enables. */
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
@@ -68,25 +67,25 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 	post_code(0x39);
 
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 	int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
 	if (!s3resume) {
 		post_code(0x40);
-		AGESAWRAPPER(amdinitpost);
+		agesawrapper_amdinitpost();
 		post_code(0x41);
-		AGESAWRAPPER(amdinitenv);
+		agesawrapper_amdinitenv();
 		disable_cache_as_ram();
 	} else {		/* S3 detect */
 		printk(BIOS_INFO, "S3 detected\n");
 
 		post_code(0x60);
-		AGESAWRAPPER(amdinitresume);
+		agesawrapper_amdinitresume();
 
 		agesawrapper_amdinitcpuio();
-		AGESAWRAPPER(amds3laterestore);
+		agesawrapper_amds3laterestore();
 
 		post_code(0x61);
 		prepare_for_resume();
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index fbe60fc911..5434ed3fe2 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -32,7 +32,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include <superio/fintek/common/fintek.h>
 #include <superio/fintek/f81865f/f81865f.h>
@@ -80,29 +79,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x35);
-	AGESAWRAPPER(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	post_code(0x39);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
 	if (!s3resume) {
 		post_code(0x40);
-		AGESAWRAPPER(amdinitpost);
+		agesawrapper_amdinitpost();
 
 		post_code(0x42);
-		AGESAWRAPPER(amdinitenv);
+		agesawrapper_amdinitenv();
 
 	} else { 			/* S3 detect */
 		printk(BIOS_INFO, "S3 detected\n");
 
 		post_code(0x60);
-		AGESAWRAPPER(amdinitresume);
+		agesawrapper_amdinitresume();
 
-		AGESAWRAPPER(amds3laterestore);
+		agesawrapper_amds3laterestore();
 
 		post_code(0x61);
 		prepare_for_resume();
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c
index a64ba603e2..7dcd9b206c 100644
--- a/src/mainboard/amd/south_station/romstage.c
+++ b/src/mainboard/amd/south_station/romstage.c
@@ -32,7 +32,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include <superio/fintek/common/fintek.h>
 #include <superio/fintek/f81865f/f81865f.h>
@@ -75,19 +74,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x35);
-	AGESAWRAPPER(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	post_code(0x39);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	post_code(0x40);
-	AGESAWRAPPER(amdinitpost);
+	agesawrapper_amdinitpost();
 
 	post_code(0x41);
-	AGESAWRAPPER(amdinitenv);
+	agesawrapper_amdinitenv();
 
 	post_code(0x50);
 	copy_and_run();
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index 6a300d610d..193454542c 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -31,7 +31,6 @@
 #include <console/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/lapic.h"
 #include "southbridge/amd/agesa/hudson/hudson.h"
@@ -48,7 +47,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u8 byte;
 	pci_devfn_t dev;
 
-	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	/* Set LPC decode enables. */
 	dev = PCI_DEV(0, 0x14, 3);
@@ -82,25 +81,25 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 	post_code(0x39);
 
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 	int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
 	if (!s3resume) {
 		post_code(0x40);
-		AGESAWRAPPER(amdinitpost);
+		agesawrapper_amdinitpost();
 		post_code(0x41);
-		AGESAWRAPPER(amdinitenv);
+		agesawrapper_amdinitenv();
 		disable_cache_as_ram();
 	} else {		/* S3 detect */
 		printk(BIOS_INFO, "S3 detected\n");
 
 		post_code(0x60);
-		AGESAWRAPPER(amdinitresume);
+		agesawrapper_amdinitresume();
 
 		agesawrapper_amdinitcpuio();
-		AGESAWRAPPER(amds3laterestore);
+		agesawrapper_amds3laterestore();
 
 		post_code(0x61);
 		prepare_for_resume();
diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
index 682a76ea2c..f2bcccc519 100644
--- a/src/mainboard/amd/torpedo/romstage.c
+++ b/src/mainboard/amd/torpedo/romstage.c
@@ -29,7 +29,6 @@
 #include <console/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include <superio/smsc/kbc1100/kbc1100.h>
 #include "cpu/x86/lapic.h"
@@ -45,7 +44,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 val;
 
 	post_code(0x35);
-	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
@@ -72,13 +71,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x36);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	post_code(0x38);
-	AGESAWRAPPER(amdinitpost);
+	agesawrapper_amdinitpost();
 
 	post_code(0x39);
 	printk(BIOS_DEBUG, "sb_before_pci_init ");
@@ -86,7 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x40);
-	AGESAWRAPPER(amdinitenv);
+	agesawrapper_amdinitenv();
 
 	post_code(0x43);
 	copy_and_run();
diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c
index 7745338251..ac583dd33d 100644
--- a/src/mainboard/amd/union_station/romstage.c
+++ b/src/mainboard/amd/union_station/romstage.c
@@ -32,7 +32,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/lapic.h"
 #include <sb_cimx.h>
@@ -69,19 +68,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x35);
-	AGESAWRAPPER(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	post_code(0x39);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	post_code(0x40);
-	AGESAWRAPPER(amdinitpost);
+	agesawrapper_amdinitpost();
 
 	post_code(0x41);
-	AGESAWRAPPER(amdinitenv);
+	agesawrapper_amdinitenv();
 
 	post_code(0x50);
 	copy_and_run();
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index f297da68df..c7c71a1e96 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -31,7 +31,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include <superio/nuvoton/common/nuvoton.h>
 #include <superio/nuvoton/nct5572d/nct5572d.h>
@@ -75,19 +74,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x35);
-	AGESAWRAPPER(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	post_code(0x39);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	post_code(0x40);
-	AGESAWRAPPER(amdinitpost);
+	agesawrapper_amdinitpost();
 
 	post_code(0x41);
-	AGESAWRAPPER(amdinitenv);
+	agesawrapper_amdinitenv();
 
 	post_code(0x50);
 	copy_and_run();
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c
index 24fa1944a3..3d1458bed1 100644
--- a/src/mainboard/asrock/imb-a180/romstage.c
+++ b/src/mainboard/asrock/imb-a180/romstage.c
@@ -31,7 +31,6 @@
 #include <console/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/lapic.h"
 #include "southbridge/amd/agesa/hudson/hudson.h"
@@ -56,7 +55,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	//outb(0xD2, 0xcd6);
 	//outb(0x00, 0xcd7);
 
-	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	/* Set LPC decode enables. */
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
@@ -105,29 +104,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		val = inb(0xcd6);
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 	post_code(0x38);
 	printk(BIOS_DEBUG, "Got past yangtze_early_setup\n");
 
 	post_code(0x39);
 
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 	int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
 	if (!s3resume) {
 		post_code(0x40);
-		AGESAWRAPPER(amdinitpost);
+		agesawrapper_amdinitpost();
 		post_code(0x41);
-		AGESAWRAPPER(amdinitenv);
+		agesawrapper_amdinitenv();
 		/* TODO: Disable cache is not ok. */
 		disable_cache_as_ram();
 	} else { /* S3 detect */
 		printk(BIOS_INFO, "S3 detected\n");
 
 		post_code(0x60);
-		AGESAWRAPPER(amdinitresume);
+		agesawrapper_amdinitresume();
 
 		agesawrapper_amdinitcpuio();
-		AGESAWRAPPER(amds3laterestore);
+		agesawrapper_amds3laterestore();
 
 		post_code(0x61);
 		prepare_for_resume();
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index 57450ee3fa..fbc89a7fa2 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -19,7 +19,6 @@
  */
 
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 
 #include <arch/acpi.h>
 #include <arch/cpu.h>
@@ -76,7 +75,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	hudson_lpc_port80();
 #endif
 
-	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 
@@ -128,24 +127,24 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 	post_code(0x39);
 
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 	int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
 	if (!s3resume) {
 		post_code(0x40);
-		AGESAWRAPPER(amdinitpost);
+		agesawrapper_amdinitpost();
 		post_code(0x41);
-		AGESAWRAPPER(amdinitenv);
+		agesawrapper_amdinitenv();
 		disable_cache_as_ram();
 	} else {		/* S3 detect */
 		printk(BIOS_INFO, "S3 detected\n");
 
 		post_code(0x60);
-		AGESAWRAPPER(amdinitresume);
+		agesawrapper_amdinitresume();
 		agesawrapper_amdinitcpuio();
-		AGESAWRAPPER(amds3laterestore);
+		agesawrapper_amds3laterestore();
 
 		post_code(0x61);
 		prepare_for_resume();
diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c
index 95c7041b08..92b52929d5 100644
--- a/src/mainboard/gizmosphere/gizmo/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo/romstage.c
@@ -33,7 +33,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include <cpu/x86/cache.h>
 #include <sb_cimx.h>
@@ -88,29 +87,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x35);
-	AGESAWRAPPER(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	post_code(0x39);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
 	if (!s3resume) {
 		post_code(0x40);
-		AGESAWRAPPER(amdinitpost);
+		agesawrapper_amdinitpost();
 
 		post_code(0x42);
-		AGESAWRAPPER(amdinitenv);
+		agesawrapper_amdinitenv();
 
 	} else { 			/* S3 detect */
 		printk(BIOS_INFO, "S3 detected\n");
 
 		post_code(0x60);
-		AGESAWRAPPER(amdinitresume);
+		agesawrapper_amdinitresume();
 
-		AGESAWRAPPER(amds3laterestore);
+		agesawrapper_amds3laterestore();
 
 		post_code(0x61);
 		prepare_for_resume();
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
index 449a8c1a59..9411ac87e2 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
@@ -18,7 +18,6 @@
  */
 
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 
 #include <arch/acpi.h>
 #include <arch/cpu.h>
@@ -39,7 +38,7 @@
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
-	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	/* Set LPC decode enables. */
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
@@ -64,25 +63,25 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 	post_code(0x39);
 
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 	int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
 	if (!s3resume) {
 		post_code(0x40);
-		AGESAWRAPPER(amdinitpost);
+		agesawrapper_amdinitpost();
 		post_code(0x41);
-		AGESAWRAPPER(amdinitenv);
+		agesawrapper_amdinitenv();
 		disable_cache_as_ram();
 	} else {		/* S3 detect */
 		printk(BIOS_INFO, "S3 detected\n");
 
 		post_code(0x60);
-		AGESAWRAPPER(amdinitresume);
+		agesawrapper_amdinitresume();
 
 		agesawrapper_amdinitcpuio();
-		AGESAWRAPPER(amds3laterestore);
+		agesawrapper_amds3laterestore();
 
 		post_code(0x61);
 		prepare_for_resume();
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index 30215ce907..534bdc44bf 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -19,7 +19,6 @@
  */
 
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 
 #include <arch/acpi.h>
 #include <arch/cpu.h>
@@ -96,29 +95,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x35);
-	AGESAWRAPPER(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	post_code(0x39);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
 	if (!s3resume) {
 		post_code(0x40);
-		AGESAWRAPPER(amdinitpost);
+		agesawrapper_amdinitpost();
 
 		post_code(0x42);
-		AGESAWRAPPER(amdinitenv);
+		agesawrapper_amdinitenv();
 
 	} else { 			/* S3 detect */
 		printk(BIOS_INFO, "S3 detected\n");
 
 		post_code(0x60);
-		AGESAWRAPPER(amdinitresume);
+		agesawrapper_amdinitresume();
 
-		AGESAWRAPPER(amds3laterestore);
+		agesawrapper_amds3laterestore();
 
 		post_code(0x61);
 		prepare_for_resume();
diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c
index 449a8c1a59..9411ac87e2 100644
--- a/src/mainboard/lenovo/g505s/romstage.c
+++ b/src/mainboard/lenovo/g505s/romstage.c
@@ -18,7 +18,6 @@
  */
 
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 
 #include <arch/acpi.h>
 #include <arch/cpu.h>
@@ -39,7 +38,7 @@
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
-	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	/* Set LPC decode enables. */
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
@@ -64,25 +63,25 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 	post_code(0x39);
 
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 	int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
 	if (!s3resume) {
 		post_code(0x40);
-		AGESAWRAPPER(amdinitpost);
+		agesawrapper_amdinitpost();
 		post_code(0x41);
-		AGESAWRAPPER(amdinitenv);
+		agesawrapper_amdinitenv();
 		disable_cache_as_ram();
 	} else {		/* S3 detect */
 		printk(BIOS_INFO, "S3 detected\n");
 
 		post_code(0x60);
-		AGESAWRAPPER(amdinitresume);
+		agesawrapper_amdinitresume();
 
 		agesawrapper_amdinitcpuio();
-		AGESAWRAPPER(amds3laterestore);
+		agesawrapper_amds3laterestore();
 
 		post_code(0x61);
 		prepare_for_resume();
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c
index 02f4bc7c49..c4bf978553 100644
--- a/src/mainboard/lippert/frontrunner-af/romstage.c
+++ b/src/mainboard/lippert/frontrunner-af/romstage.c
@@ -32,7 +32,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include <superio/smsc/smscsuperio/smscsuperio.h>
 #include "cpu/x86/lapic.h"
@@ -79,33 +78,33 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x35);
-	AGESAWRAPPER(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	post_code(0x39);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
 	if (!s3resume) {
 		post_code(0x40);
 		/* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all
 		 * hang, looks like DRAM re-init goes wrong, don't know why. */
-		val = AGESAWRAPPER(amdinitpost);
+		val = agesawrapper_amdinitpost();
 		if (val == 7) /* fatal, amdinitenv below is going to hang */
 			outb(0x06, 0x0cf9); /* reset system harder instead */
 
 		post_code(0x42);
-		AGESAWRAPPER(amdinitenv);
+		agesawrapper_amdinitenv();
 
 	} else { 			/* S3 detect */
 		printk(BIOS_INFO, "S3 detected\n");
 
 		post_code(0x60);
-		AGESAWRAPPER(amdinitresume);
+		agesawrapper_amdinitresume();
 
-		AGESAWRAPPER(amds3laterestore);
+		agesawrapper_amds3laterestore();
 
 		post_code(0x61);
 		prepare_for_resume();
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index 2714d7f0e1..9d99894383 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -32,7 +32,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627dhg/w83627dhg.h>
@@ -80,33 +79,33 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x35);
-	AGESAWRAPPER(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	post_code(0x39);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
 	if (!s3resume) {
 		post_code(0x40);
 		/* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all
 		 * hang, looks like DRAM re-init goes wrong, don't know why. */
-		val = AGESAWRAPPER(amdinitpost);
+		val = agesawrapper_amdinitpost();
 		if (val == 7) /* fatal, amdinitenv below is going to hang */
 			outb(0x06, 0x0cf9); /* reset system harder instead */
 
 		post_code(0x42);
-		AGESAWRAPPER(amdinitenv);
+		agesawrapper_amdinitenv();
 
 	} else { 			/* S3 detect */
 		printk(BIOS_INFO, "S3 detected\n");
 
 		post_code(0x60);
-		AGESAWRAPPER(amdinitresume);
+		agesawrapper_amdinitresume();
 
-		AGESAWRAPPER(amds3laterestore);
+		agesawrapper_amds3laterestore();
 
 		post_code(0x61);
 		prepare_for_resume();
diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c
index d584a4cd7c..9c48601f6a 100644
--- a/src/mainboard/supermicro/h8qgi/romstage.c
+++ b/src/mainboard/supermicro/h8qgi/romstage.c
@@ -28,7 +28,6 @@
 #include "cpu/x86/lapic.h"
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "northbridge/amd/agesa/family10/reset_test.h"
 #include <nb_cimx.h>
 #include <sb_cimx.h>
@@ -46,7 +45,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 val;
 
 	post_code(0x30);
-	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+	agesawrapper_amdinitmmio();
 	post_code(0x31);
 
 	/* Halt if there was a built in self test failure */
@@ -66,7 +65,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x38);
@@ -81,7 +80,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		sb_Poweron_Init();
 	}
 	post_code(0x3B);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	post_code(0x3C);
 	/* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default.
@@ -101,10 +100,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	}
 
 	post_code(0x40);
-	AGESAWRAPPER(amdinitpost);
+	agesawrapper_amdinitpost();
 
 	post_code(0x41);
-	AGESAWRAPPER(amdinitenv);
+	agesawrapper_amdinitenv();
 	post_code(0x42);
 
 	post_code(0x50);
diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c
index c67a9265af..2f4c828db5 100644
--- a/src/mainboard/supermicro/h8scm/romstage.c
+++ b/src/mainboard/supermicro/h8scm/romstage.c
@@ -28,7 +28,6 @@
 #include "cpu/x86/lapic.h"
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "northbridge/amd/agesa/family10/reset_test.h"
 #include <nb_cimx.h>
 #include <sb_cimx.h>
@@ -45,7 +44,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 val;
 
 	post_code(0x30);
-	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+	agesawrapper_amdinitmmio();
 	post_code(0x31);
 
 	/* Halt if there was a built in self test failure */
@@ -65,7 +64,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x38);
@@ -80,7 +79,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		sb_Poweron_Init();
 	}
 	post_code(0x3B);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	post_code(0x3C);
 	nb_Ht_Init();
@@ -95,10 +94,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	}
 
 	post_code(0x40);
-	AGESAWRAPPER(amdinitpost);
+	agesawrapper_amdinitpost();
 
 	post_code(0x41);
-	AGESAWRAPPER(amdinitenv);
+	agesawrapper_amdinitenv();
 	post_code(0x42);
 
 	post_code(0x50);
diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c
index a0e8bfd33d..8587ed1797 100644
--- a/src/mainboard/tyan/s8226/romstage.c
+++ b/src/mainboard/tyan/s8226/romstage.c
@@ -28,7 +28,6 @@
 #include "cpu/x86/lapic.h"
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "northbridge/amd/agesa/family10/reset_test.h"
 #include <nb_cimx.h>
 #include <sb_cimx.h>
@@ -44,7 +43,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 val;
 
 	post_code(0x30);
-	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+	agesawrapper_amdinitmmio();
 	post_code(0x31);
 
 	/* For serial port. */
@@ -69,7 +68,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x38);
@@ -84,7 +83,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		sb_Poweron_Init();
 	}
 	post_code(0x3B);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	post_code(0x3C);
 	/* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default.
@@ -104,10 +103,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	}
 
 	post_code(0x40);
-	AGESAWRAPPER(amdinitpost);
+	agesawrapper_amdinitpost();
 
 	post_code(0x41);
-	AGESAWRAPPER(amdinitenv);
+	agesawrapper_amdinitenv();
 	post_code(0x42);
 
 	post_code(0x50);