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authorBora Guvendik <bora.guvendik@intel.com>2020-03-10 17:50:28 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-03-20 09:39:27 +0000
commit12b835050f0af9341b257560b60a8060c8fad328 (patch)
treeb0b9ccdfc955c7f178f2dc2cf88462a19e15a856 /src/mainboard
parent70ea3b9141ee92177c1a1185a7e6a468fd59bc85 (diff)
soc/intel: Enable GPIO functions in verstage
Enable GPIO functionality in verstage so platforms can read a PCH GPIO in verstage to determine recovery mode. BUG=b:151102807 TEST=make build successful Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I4e3b9da307dcf59ab251d8a6a5e09c2a3cfc59fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/39501 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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