diff options
| author | Ryan Lin <ryan.lin@intel.com> | 2015-12-25 10:54:44 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-01-19 16:24:13 +0100 |
| commit | 0691f25e53e2567e3afd455e7e3dc38fc10147f3 (patch) | |
| tree | 4a12bc87ed212c9aafa06ec922edc4f1c3ee1664 /src/mainboard | |
| parent | bc58a878cd0ae34ca9ebfc66bfc8ca440e58a0eb (diff) | |
google/chell: Enable eMMC HS400 mode
Hynix eMMC can now run under HS400 mode.
BUG=chrome-os-partner:47647
TEST=run consective boot 100 times on Chell EVT Hynix SKU, and
MMC errors didn't happen.
BRANCH=none
Change-Id: Icb6fc03d0510d2c5aeb5b08ed7189e954ab39a72
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9966c430a508a13cf1a617f485a48866bec161ca
Original-Change-Id: I6bec88f5c2813131a693ddba5523a9d43b2ebd45
Original-Signed-off-by: Ryan Lin <ryan.lin@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319627
Original-Commit-Ready: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13003
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/chell/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index 81df06f083..ceb11607ed 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -35,7 +35,7 @@ chip soc/intel/skylake register "SmbusEnable" = "1" register "Cio2Enable" = "0" register "ScsEmmcEnabled" = "1" - register "ScsEmmcHs400Enabled" = "0" + register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "0" register "IshEnable" = "0" register "PttSwitch" = "0" |