Rename {CPU|NB|SB}/amd/*_wrapper folders

This change renames the cpu/amd/agesa_wrapper, northbridge/
amd/agesa_wrapper, and southbridge/amd/cimx_wrapper folders
to {cpu|NB}/amd/agesa and {SB}/amd/agesa to shorten and
simplify the folder names.
There is also a fix to vendorcode/amd/agesa/lib/amdlib.c to
append "ull" to a trio of 64-bit hexadecimal constants to
allow abuild to run successfully.

Change-Id: I2455e0afb0361ad2e11da2b869ffacbd552cb715
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/51
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

9 files changed, 43 insertions, 43 deletions

diff --git a/src/mainboard/advansus/a785e-i/Kconfig b/src/mainboard/advansus/a785e-i/Kconfig
index ab3104bdaa..6e3a4ab528 100644
--- a/src/mainboard/advansus/a785e-i/Kconfig
+++ b/src/mainboard/advansus/a785e-i/Kconfig
@@ -9,7 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select QRANK_DIMM_SUPPORT
 	select NORTHBRIDGE_AMD_AMDFAM10
 	select SOUTHBRIDGE_AMD_RS780
-	select SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
+	select SOUTHBRIDGE_AMD_CIMX_SB800
 	select SUPERIO_WINBOND_W83627HF #COM1, COM2
 	#select SUPERIO_FINTEK_F81216AD #COM3, COM4
 	select HAVE_BUS_CONFIG
diff --git a/src/mainboard/advansus/a785e-i/devicetree.cb b/src/mainboard/advansus/a785e-i/devicetree.cb
index 74f50d02fa..25a1f646d8 100644
--- a/src/mainboard/advansus/a785e-i/devicetree.cb
+++ b/src/mainboard/advansus/a785e-i/devicetree.cb
@@ -34,7 +34,7 @@ chip northbridge/amd/amdfam10/root_complex
 					register "gfx_pcie_config" = "3" # 1x8 GFX on Lanes 8-15
 					register "gfx_ddi_config" = "1"  # Lanes 0-3 DDI_SL
 				end
-				chip southbridge/amd/cimx_wrapper/sb800 # it is under NB/SB Link, but on the same pci bus
+				chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pci bus
 					device pci 11.0 on end # SATA
 					device pci 12.0 on end # USB
 					device pci 12.2 on end # USB
@@ -112,7 +112,7 @@ chip northbridge/amd/amdfam10/root_complex
 					#register "gpp_configuration" = "3" #2:1:1:0
 					register "gpp_configuration" = "4" #1:1:1:1
 					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-				end	#southbridge/amd/cimx_wrapper/sb800
+				end	#southbridge/amd/cimx/sb800
 			end #  device pci 18.0
 
 			device pci 18.1 on end
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index f2544e70ec..9e31779118 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -49,7 +49,7 @@
 #include "southbridge/amd/rs780/early_setup.c"
 #include <SbEarly.h>
 #include <SBPLATFORM.h> /* SB OEM constants */
-#include <southbridge/amd/cimx_wrapper/sb800/smbus.h>
+#include <southbridge/amd/cimx/sb800/smbus.h>
 #include "northbridge/amd/amdfam10/debug.c"
 
 static void activate_spd_rom(const struct mem_controller *ctrl)
diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig
index 8e4eca96b5..eb43d6d59e 100644
--- a/src/mainboard/amd/inagua/Kconfig
+++ b/src/mainboard/amd/inagua/Kconfig
@@ -24,10 +24,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy
   select ARCH_X86
         select DIMM_DDR3
         select DIMM_UNREGISTERED
-  select CPU_AMD_AGESA_WRAPPER_FAMILY14
-  select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX
-  select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
-  select SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
+  select CPU_AMD_AGESA_FAMILY14
+  select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX
+  select NORTHBRIDGE_AMD_AGESA_FAMILY14
+  select SOUTHBRIDGE_AMD_CIMX_SB800
   select SUPERIO_SMSC_KBC1100
   select BOARD_HAS_FADT
         select HAVE_BUS_CONFIG
diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb
index acae2ca42b..67be34e8be 100644
--- a/src/mainboard/amd/inagua/devicetree.cb
+++ b/src/mainboard/amd/inagua/devicetree.cb
@@ -16,17 +16,17 @@
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
-chip northbridge/amd/agesa_wrapper/family14/root_complex
+chip northbridge/amd/agesa/family14/root_complex
         device lapic_cluster 0 on
-                chip cpu/amd/agesa_wrapper/family14
+                chip cpu/amd/agesa/family14
                   device lapic 0 on end
                 end
         end
         device pci_domain 0 on
                 subsystemid 0x1022 0x1510 inherit
-                chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
+                chip northbridge/amd/agesa/family14 # CPU side of HT root complex
 #                       device pci 18.0 on #  northbridge
-                                chip northbridge/amd/agesa_wrapper/family14 # PCI side of HT root complex
+                                chip northbridge/amd/agesa/family14 # PCI side of HT root complex
                                         device pci 0.0 on end # Root Complex
                                         device pci 1.0 on end # Internal Graphics P2P bridge
                                         device pci 1.1 on end # Internal Multimedia
@@ -35,9 +35,9 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
                                         device pci 6.0 on end # PCIE P2P bridge 0x9606
                                         device pci 7.0 off end # PCIE P2P bridge 0x9607
                                         device pci 8.0 off end # NB/SB Link P2P bridge
-                                end # agesa_wrapper northbridge
+                                end # agesa northbridge
 
-                                chip southbridge/amd/cimx_wrapper/sb800 # it is under NB/SB Link, but on the same pri bus
+                                chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
                                         device pci 11.0 on end # SATA
                                         device pci 12.0 on end # USB
                                         device pci 12.1 on end # USB
@@ -73,7 +73,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
 					device pci 15.3 on end # PCIe PortD
 					register "gpp_configuration" = "4" #1:1:1:1
 		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-				end	#southbridge/amd/cimx_wrapper/sb800
+				end	#southbridge/amd/cimx/sb800
 #                       end #  device pci 18.0
 # These seem unnecessary
                         device pci 18.0 on end
@@ -85,7 +85,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
                         device pci 18.5 on end
                         device pci 18.6 on end
                         device pci 18.7 on end
-                end #chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
+                end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
         end #pci_domain
-end #northbridge/amd/agesa_wrapper/family14/root_complex
+end #northbridge/amd/agesa/family14/root_complex
 
diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig
index 54db652c6a..034984c80f 100644
--- a/src/mainboard/amd/persimmon/Kconfig
+++ b/src/mainboard/amd/persimmon/Kconfig
@@ -22,10 +22,10 @@ if BOARD_AMD_PERSIMMON
 config BOARD_SPECIFIC_OPTIONS # dummy
         def_bool y
   select ARCH_X86
-  select CPU_AMD_AGESA_WRAPPER_FAMILY14
-  select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX
-  select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
-  select SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
+  select CPU_AMD_AGESA_FAMILY14
+  select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX
+  select NORTHBRIDGE_AMD_AGESA_FAMILY14
+  select SOUTHBRIDGE_AMD_CIMX_SB800
 	select SUPERIO_FINTEK_F81865F
   select BOARD_HAS_FADT
         select HAVE_BUS_CONFIG
diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb
index 3a9ec400a6..a6763884c7 100644
--- a/src/mainboard/amd/persimmon/devicetree.cb
+++ b/src/mainboard/amd/persimmon/devicetree.cb
@@ -16,17 +16,17 @@
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
-chip northbridge/amd/agesa_wrapper/family14/root_complex
+chip northbridge/amd/agesa/family14/root_complex
         device lapic_cluster 0 on
-                chip cpu/amd/agesa_wrapper/family14
+                chip cpu/amd/agesa/family14
                   device lapic 0 on end
                 end
         end
         device pci_domain 0 on
                 subsystemid 0x1022 0x1510 inherit
-                chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
+                chip northbridge/amd/agesa/family14 # CPU side of HT root complex
 #                       device pci 18.0 on #  northbridge
-                                chip northbridge/amd/agesa_wrapper/family14 # PCI side of HT root complex
+                                chip northbridge/amd/agesa/family14 # PCI side of HT root complex
                                         device pci 0.0 on end # Root Complex
                                         device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
                                         device pci 1.1 on end # Internal Multimedia
@@ -35,9 +35,9 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
                                         device pci 6.0 off end # PCIE P2P bridge 0x9606
                                         device pci 7.0 off end # PCIE P2P bridge 0x9607
                                         device pci 8.0 off end # NB/SB Link P2P bridge
-                                end # agesa_wrapper northbridge
+                                end # agesa northbridge
 
-                                chip southbridge/amd/cimx_wrapper/sb800 # it is under NB/SB Link, but on the same pri bus
+                                chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
                                         device pci 11.0 on end # SATA
                                         device pci 12.0 on end # USB
                                         device pci 12.1 on end # USB
@@ -89,7 +89,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
 					device pci 15.3 off end # PCIe PortD
 					register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
 		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-				end	#southbridge/amd/cimx_wrapper/sb800
+				end	#southbridge/amd/cimx/sb800
 #                       end #  device pci 18.0
 # These seem unnecessary
                         device pci 18.0 on end
@@ -101,7 +101,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
                         device pci 18.5 on end
                         device pci 18.6 on end
                         device pci 18.7 on end
-                end #chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
+                end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
         end #pci_domain
-end #northbridge/amd/agesa_wrapper/family14/root_complex
+end #northbridge/amd/agesa/family14/root_complex
 
diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig
index fdcc3c9ab3..e6153c01f2 100644
--- a/src/mainboard/asrock/e350m1/Kconfig
+++ b/src/mainboard/asrock/e350m1/Kconfig
@@ -22,10 +22,10 @@ if BOARD_ASROCK_E350M1
 config BOARD_SPECIFIC_OPTIONS # dummy
         def_bool y
   select ARCH_X86
-  select CPU_AMD_AGESA_WRAPPER_FAMILY14
-  select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX
-  select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
-  select SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
+  select CPU_AMD_AGESA_FAMILY14
+  select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX
+  select NORTHBRIDGE_AMD_AGESA_FAMILY14
+  select SOUTHBRIDGE_AMD_CIMX_SB800
 	select SUPERIO_WINBOND_W83627HF
   select BOARD_HAS_FADT
         select HAVE_BUS_CONFIG
diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb
index 43607ebb02..5983ed2148 100644
--- a/src/mainboard/asrock/e350m1/devicetree.cb
+++ b/src/mainboard/asrock/e350m1/devicetree.cb
@@ -16,17 +16,17 @@
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
-chip northbridge/amd/agesa_wrapper/family14/root_complex
+chip northbridge/amd/agesa/family14/root_complex
         device lapic_cluster 0 on
-                chip cpu/amd/agesa_wrapper/family14
+                chip cpu/amd/agesa/family14
                   device lapic 0 on end
                 end
         end
         device pci_domain 0 on
                 subsystemid 0x1022 0x1510 inherit
-                chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
+                chip northbridge/amd/agesa/family14 # CPU side of HT root complex
 #                       device pci 18.0 on #  northbridge
-                                chip northbridge/amd/agesa_wrapper/family14 # PCI side of HT root complex
+                                chip northbridge/amd/agesa/family14 # PCI side of HT root complex
                                         device pci 0.0 on end # Root Complex
                                         device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
                                         device pci 1.1 on end # Internal Multimedia
@@ -35,9 +35,9 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
                                         device pci 6.0 off end # PCIE P2P bridge 0x9606
                                         device pci 7.0 off end # PCIE P2P bridge 0x9607
                                         device pci 8.0 off end # NB/SB Link P2P bridge
-                                end # agesa_wrapper northbridge
+                                end # agesa northbridge
 
-                                chip southbridge/amd/cimx_wrapper/sb800 # it is under NB/SB Link, but on the same pri bus
+                                chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
                                         device pci 11.0 on end # SATA
                                         device pci 12.0 on end # USB
                                         device pci 12.1 on end # USB
@@ -113,7 +113,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
 					register "gpp_configuration" = "4"
 
  		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-				end	#southbridge/amd/cimx_wrapper/sb800
+				end	#southbridge/amd/cimx/sb800
 #                       end #  device pci 18.0
 # These seem unnecessary
                         device pci 18.0 on end
@@ -125,7 +125,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
                         device pci 18.5 on end
                         device pci 18.6 on end
                         device pci 18.7 on end
-                end #chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
+                end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
         end #pci_domain
-end #northbridge/amd/agesa_wrapper/family14/root_complex
+end #northbridge/amd/agesa/family14/root_complex