diff options
| author | David Wu <david_wu@quanta.corp-partner.google.com> | 2022-07-05 17:44:56 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-07 15:52:40 +0000 |
| commit | f2df9490a85575eb7f8fcedefd1dbff85a0905c2 (patch) | |
| tree | fb17e1522ee7a4782a3d2e1623f543e772de1cca /src/mainboard | |
| parent | 48827fdcef423881d72a1327f2d6f3659a6e7856 (diff) | |
mb/google/brask/var/kuldax: modify ddi_ports_config
Modify ddi_ports_config based on schematic.
DDI_PORT_A = DP
DDI_PORT_B = HDMI
DDI_PORT_1 = Type-C DP
DDI_PORT_3 = HDMI
BUG=b:237419696
TEST=Boot to Chrome OS and check all display port working
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I7c0458f0dbd4637b91af9e01664073e1f8a7a614
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/kuldax/overridetree.cb | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/kuldax/overridetree.cb b/src/mainboard/google/brya/variants/kuldax/overridetree.cb index 50b2e39f47..d31c2be69f 100644 --- a/src/mainboard/google/brya/variants/kuldax/overridetree.cb +++ b/src/mainboard/google/brya/variants/kuldax/overridetree.cb @@ -11,6 +11,13 @@ chip soc/intel/alderlake [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, }" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD, + [DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + device domain 0 on device ref dtt on chip drivers/intel/dptf |