From f2df9490a85575eb7f8fcedefd1dbff85a0905c2 Mon Sep 17 00:00:00 2001 From: David Wu Date: Tue, 5 Jul 2022 17:44:56 +0800 Subject: mb/google/brask/var/kuldax: modify ddi_ports_config Modify ddi_ports_config based on schematic. DDI_PORT_A = DP DDI_PORT_B = HDMI DDI_PORT_1 = Type-C DP DDI_PORT_3 = HDMI BUG=b:237419696 TEST=Boot to Chrome OS and check all display port working Signed-off-by: David Wu Change-Id: I7c0458f0dbd4637b91af9e01664073e1f8a7a614 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65660 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/kuldax/overridetree.cb | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/google/brya/variants/kuldax/overridetree.cb b/src/mainboard/google/brya/variants/kuldax/overridetree.cb index 50b2e39f47..d31c2be69f 100644 --- a/src/mainboard/google/brya/variants/kuldax/overridetree.cb +++ b/src/mainboard/google/brya/variants/kuldax/overridetree.cb @@ -11,6 +11,13 @@ chip soc/intel/alderlake [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, }" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD, + [DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + device domain 0 on device ref dtt on chip drivers/intel/dptf -- cgit v1.2.3