google/fizz: Enable cr50 over SPI

We are changing the bootstraps in the EVTs so that the SOC
communicates with cr50 over SPI instead of cr50.  SPI is more reliable
than I2C.  Thus, disabling cr50 over I2C and enabling cr50 over SPI.

BUG=b:65056998, b:62456589
BRANCH=None
TEST=make sure that we can boot into kernel
     run cold_reset and warm_reset and make sure both
     boot successfully.
CQ-DEPEND=CL:714237

Change-Id: I85b9a61f0305e3c7ccada79d7702234a285a6d2a
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/21970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

0 files changed, 0 insertions, 0 deletions