diff options
author | Stefan Reinauer <reinauer@chromium.org> | 2014-12-17 13:31:54 -0800 |
---|---|---|
committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2014-12-18 02:13:53 +0100 |
commit | e4c73bb5baac96ca49c5dea1916dfcfbd1af2e26 (patch) | |
tree | fd8516b36fac98cec70b45724c2324cc2329ac52 /src/mainboard/via/epia | |
parent | 5878bbd935c8cbd7c6d25ef72a5460f3262119e7 (diff) |
Drop VIA Epia mainboard
.. and also drop the northbridge and southbridge used by the board.
This is one of the last boards to not use ROMCC for romstage. Let's
get rid of it.
Change-Id: I0a864b2c4ce3eeb7d3e199944eedef0cd71a85e6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7853
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/mainboard/via/epia')
-rw-r--r-- | src/mainboard/via/epia/Kconfig | 26 | ||||
-rw-r--r-- | src/mainboard/via/epia/board_info.txt | 2 | ||||
-rw-r--r-- | src/mainboard/via/epia/cmos.layout | 72 | ||||
-rw-r--r-- | src/mainboard/via/epia/devicetree.cb | 61 | ||||
-rw-r--r-- | src/mainboard/via/epia/irq_tables.c | 36 | ||||
-rw-r--r-- | src/mainboard/via/epia/romstage.c | 95 |
6 files changed, 0 insertions, 292 deletions
diff --git a/src/mainboard/via/epia/Kconfig b/src/mainboard/via/epia/Kconfig deleted file mode 100644 index 7ee1ed8dcd..0000000000 --- a/src/mainboard/via/epia/Kconfig +++ /dev/null @@ -1,26 +0,0 @@ -if BOARD_VIA_EPIA - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_VIA_C3 - select NORTHBRIDGE_VIA_VT8601 - select SOUTHBRIDGE_VIA_VT8231 - select SUPERIO_WINBOND_W83627HF - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select BOARD_ROMSIZE_KB_256 - select ROMCC - -config MAINBOARD_DIR - string - default via/epia - -config MAINBOARD_PART_NUMBER - string - default "EPIA" - -config IRQ_SLOT_COUNT - int - default 5 - -endif # BOARD_VIA_EPIA diff --git a/src/mainboard/via/epia/board_info.txt b/src/mainboard/via/epia/board_info.txt deleted file mode 100644 index d39a82d807..0000000000 --- a/src/mainboard/via/epia/board_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -Category: mini -Board URL: http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=21 diff --git a/src/mainboard/via/epia/cmos.layout b/src/mainboard/via/epia/cmos.layout deleted file mode 100644 index 9050c3db7a..0000000000 --- a/src/mainboard/via/epia/cmos.layout +++ /dev/null @@ -1,72 +0,0 @@ -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD -7 10 Fallback_Floppy -#7 3 ROM - -checksums - -checksum 392 1007 1008 diff --git a/src/mainboard/via/epia/devicetree.cb b/src/mainboard/via/epia/devicetree.cb deleted file mode 100644 index d5e16ac008..0000000000 --- a/src/mainboard/via/epia/devicetree.cb +++ /dev/null @@ -1,61 +0,0 @@ -chip northbridge/via/vt8601 - device domain 0 on - device pci 0.0 on end # Northbridge -# device pci 0.1 on # AGP bridge - # device pci 0.0 on end # Integrated VGA -# end - chip southbridge/via/vt8231 - register "enable_native_ide" = "0" - register "enable_com_ports" = "1" - register "enable_keyboard" = "0" - device pci 11.0 on # Southbrdge - chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - end - device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GAME_MIDI_GIPO1 - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - end - end - device pci 11.1 on end # Ide - device pci 11.2 off end # Usb port 0-1 - device pci 11.3 off end # Usb port 2-3 - device pci 11.4 off end # ACPI - device pci 11.5 off end # AC97 Audio - device pci 11.6 on end # AC97 Modem - device pci 12.0 on end # Ethernet - end - end - - device cpu_cluster 0 on - chip cpu/via/c3 - device lapic 0 on end - end - end -end diff --git a/src/mainboard/via/epia/irq_tables.c b/src/mainboard/via/epia/irq_tables.c deleted file mode 100644 index 94adba1e87..0000000000 --- a/src/mainboard/via/epia/irq_tables.c +++ /dev/null @@ -1,36 +0,0 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ - -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ - 0, /* Where the interrupt router lies (bus) */ - 0x88, /* Where the interrupt router lies (dev) */ - 0x1c20, /* IRQs devoted exclusively to PCI usage */ - 0x1106, /* Vendor */ - 0x8231, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x5e, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ - { - /* 8231 ethernet */ - {0,0x90, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x1, 0}, - /* 8231 internal */ - {0,0x88, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x2, 0}, - /* PCI slot */ - {0,0xa0, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}}, 0, 0}, - {0,0x50, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x3, 0}, - {0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0}, - } -}; -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/via/epia/romstage.c b/src/mainboard/via/epia/romstage.c deleted file mode 100644 index 5e209409f4..0000000000 --- a/src/mainboard/via/epia/romstage.c +++ /dev/null @@ -1,95 +0,0 @@ -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <stdlib.h> -#include <console/console.h> -#include "northbridge/via/vt8601/raminit.h" -#include "cpu/x86/mtrr/earlymtrr.c" -#include "cpu/x86/bist.h" -#include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" -#include "lib/debug.c" -#include "southbridge/via/vt8231/early_smbus.c" -#include "southbridge/via/vt8231/early_serial.c" -#include "southbridge/via/vt8231/enable_rom.c" - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/via/vt8601/raminit.c" - -static void enable_mainboard_devices(void) -{ - device_t dev; - /* dev 0 for southbridge */ - - dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); - - if (dev == PCI_DEV_INVALID) - die("Southbridge not found!!!\n"); - - pci_write_config8(dev, 0x50, 7); - pci_write_config8(dev, 0x51, 0xff); -#if 0 - // This early setup switches IDE into compatibility mode before PCI gets - // a chance to assign I/Os - // movl $CONFIG_ADDR(0, 0x89, 0x42), %eax - // movb $0x09, %dl - // movb $0x00, %dl - // PCI_WRITE_CONFIG_BYTE - // -#endif - /* we do this here as in V2, we can not yet do raw operations - * to pci! - */ - /* changed this to work correctly on later revisions of LB. - * The original dev += 0x100; stopped working. It also appears - * that if this is not set here, but in ide_init() only, the IDE - * does not work at all. I assume it needs to be set before something else, - * possibly before enabling the IDE peripheral, or it is a timing issue. - * Ben Hewson 29 Apr 2007. - */ - - dev = pci_locate_device(PCI_ID(0x1106,0x0571), 0); - pci_write_config8(dev, 0x42, 0); -} - -static void enable_shadow_ram(void) -{ - device_t dev = 0; - unsigned char shadowreg; - - shadowreg = pci_read_config8(dev, 0x63); - /* 0xf0000-0xfffff */ - shadowreg |= 0x30; - pci_write_config8(dev, 0x63, shadowreg); -} - -#include <cpu/intel/romstage.h> -static void main(unsigned long bist) -{ - if (bist == 0) - early_mtrr_init(); - - enable_vt8231_serial(); - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - vt8231_enable_rom(); - enable_mainboard_devices(); - enable_smbus(); - enable_shadow_ram(); - - /* - this is way more generic than we need. - sdram_initialize(ARRAY_SIZE(cpu), cpu); - */ - sdram_set_registers((const struct mem_controller *) 0); - sdram_set_spd_registers((const struct mem_controller *) 0); - sdram_enable(0, (const struct mem_controller *) 0); -} |