diff options
| author | Myles Watson <mylesgw@gmail.com> | 2008-10-06 21:00:46 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2008-10-06 21:00:46 +0000 |
| commit | a643ea3beba32ed170f995b2d40169017edb1095 (patch) | |
| tree | 87cfb1e20a04c52022bf1ba6cc9c8025382ed666 /src/mainboard/tyan/s2912_fam10/resourcemap.c | |
| parent | 69e9cc4fbded07f576e8c7ca0637feb8a4f08f6c (diff) | |
Whitespace fixes.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3638 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2912_fam10/resourcemap.c')
| -rw-r--r-- | src/mainboard/tyan/s2912_fam10/resourcemap.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/tyan/s2912_fam10/resourcemap.c b/src/mainboard/tyan/s2912_fam10/resourcemap.c index 60633d5ef1..73d3d43014 100644 --- a/src/mainboard/tyan/s2912_fam10/resourcemap.c +++ b/src/mainboard/tyan/s2912_fam10/resourcemap.c @@ -161,7 +161,7 @@ static void setup_mb_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CBB, CDB, 1, 0x80), 0x000000f0, 0x00000000, @@ -217,7 +217,7 @@ static void setup_mb_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -225,7 +225,7 @@ static void setup_mb_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CBB, CDB, 1, 0xC0), 0xFE000FCC, 0x00000033, @@ -272,7 +272,7 @@ static void setup_mb_resource_map(void) // PCI_ADDR(CBB, CDB, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */ // PCI_ADDR(CBB, CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */ PCI_ADDR(CBB, CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + PCI_ADDR(CBB, CDB, 1, 0xEC), 0x0000FC88, 0x00000000, }; |