Major merge of YhLu's code from 2004/04/20: add s2875, various other updates,

cleanups. Drop "driver" code from mainboard directories and use them from the
driver directory instead


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

7 files changed, 327 insertions, 163 deletions

diff --git a/src/mainboard/tyan/s2850/Config.lb b/src/mainboard/tyan/s2850/Config.lb
index ad189c9202..4b1375f4c4 100644
--- a/src/mainboard/tyan/s2850/Config.lb
+++ b/src/mainboard/tyan/s2850/Config.lb
@@ -1,6 +1,9 @@
 uses HAVE_MP_TABLE
 uses HAVE_PIRQ_TABLE
 uses USE_FALLBACK_IMAGE
+uses LB_CKS_RANGE_START
+uses LB_CKS_RANGE_END
+uses LB_CKS_LOC
 uses MAINBOARD
 uses ARCH
 uses HARD_RESET_BUS
@@ -22,13 +25,19 @@ register "fixup_scsi" = "1"
 register "fixup_vga" = "1"
 
 
+##
+## Move the default LinuxBIOS cmos range off of AMD RTC registers
+##
+default LB_CKS_RANGE_START=49
+default LB_CKS_RANGE_END=122
+default LB_CKS_LOC=123
+
 driver mainboard.o
-driver adaptec_scsi.o
-driver promise_sata.o
-driver intel_nic.o
-driver broadcom_nic.o
+#driver adaptec_scsi.o
+#driver si_sata.o
+#driver intel_nic_ipmi.o
+#driver broadcom_nic_ipmi.o
 #object reset.o
-#object static_devices.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #
@@ -44,6 +53,7 @@ arch i386 end
 ###
 mainboardinit cpu/i386/entry16.inc
 mainboardinit cpu/i386/entry32.inc
+mainboardinit cpu/i386/bist32.inc
 ldscript /cpu/i386/entry16.lds
 ldscript /cpu/i386/entry32.lds
 #
@@ -95,9 +105,9 @@ end
 ###
 ### Setup the serial port
 ###
-#mainboardinit superiowinbond/w83627hf/setup_serial.inc
 mainboardinit pc80/serial.inc
 mainboardinit arch/i386/lib/console.inc
+mainboardinit cpu/i386/bist32_fail.inc
 #
 ####
 #### O.k. We aren't just an intermediary anymore!
@@ -114,9 +124,6 @@ mainboardinit arch/i386/lib/console.inc
 ###
 ### Romcc output
 ###
-#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
-#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
-#mainboardinit .failover.inc
 
 makerule ./failover.E
 	depends "$(MAINBOARD)/failover.c" 
@@ -125,16 +132,16 @@ end
 
 makerule ./failover.inc
 	depends "./romcc ./failover.E"
-	action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
+	action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
+end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c" 
-	action	"$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+        depends "$(MAINBOARD)/auto.c option_table.h"
+        action  "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
 end
 makerule ./auto.inc 
 	depends "./romcc ./auto.E"
-	action "./romcc -O -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E" 
-#	action	"./romcc -mcpu=k8  -O ./auto.E > auto.inc"
+	action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E" 
 end
 mainboardinit cpu/k8/enable_mmx_sse.inc
 mainboardinit ./auto.inc
@@ -143,6 +150,7 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
 ###
 ### Include the secondary Configuration files 
 ###
+
 northbridge amd/amdk8 "mc0"
         pci 0:18.0
         pci 0:18.0
@@ -162,22 +170,38 @@ northbridge amd/amdk8 "mc0"
                 pci 1:0.1 on
                 pci 1:0.2 on
                 pci 1:1.0 off
+                superio winbond/w83627hf link 1
+                        pnp 2e.0 on #  Floppy
+                                 io 0x60 = 0x3f0
+                                irq 0x70 = 6
+                                drq 0x74 = 2
+                        pnp 2e.1 off #  Parallel Port
+                                 io 0x60 = 0x378
+                                irq 0x70 = 7
+                        pnp 2e.2 on #  Com1
+                                 io 0x60 = 0x3f8
+                                irq 0x70 = 4
+                        pnp 2e.3 off #  Com2
+                                 io 0x60 = 0x2f8
+                                irq 0x70 = 3
+                        pnp 2e.5 on #  Keyboard
+                                 io 0x60 = 0x60
+                                 io 0x62 = 0x64
+                                irq 0x70 = 1
+				irq 0x72 = 12
+                        pnp 2e.6 off #  CIR
+                        pnp 2e.7 off #  GAME_MIDI_GIPO1
+                        pnp 2e.8 off #  GPIO2
+                        pnp 2e.9 off #  GPIO3
+                        pnp 2e.a off #  ACPI
+                        pnp 2e.b on  #  HW Monitor
+				 io 0x60 = 0x290
+                end
         end
 end
 
-#northbridge amd/amdk8
-#end
-#southbridge amd/amd8111 "amd8111"
-#end
-#mainboardinit archi386/smp/secondary.inc
-#superio NSC/pc87360
-#	register "com1" = "{1}"
-#	register "lpt" = "{1}"
-#end
 dir /pc80
-##dir /src/superio/winbond/w83627hf
 #dir /bioscall
-#dir /cpu/k8
 cpu k8 "cpu0"
   register "up" = "{.chip = &amd8111, .ht_width=8, .ht_speed=200}"
 end
diff --git a/src/mainboard/tyan/s2850/auto.c b/src/mainboard/tyan/s2850/auto.c
index 84d9f21a39..8dc498ce14 100644
--- a/src/mainboard/tyan/s2850/auto.c
+++ b/src/mainboard/tyan/s2850/auto.c
@@ -1,104 +1,117 @@
 #define ASSEMBLY 1
 #include <stdint.h>
 #include <device/pci_def.h>
-#include <cpu/p6/apic.h>
 #include <arch/io.h>
+#include <device/pnp_def.h>
 #include <arch/romcc_io.h>
+#include <arch/smp/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
-#include "northbridge/amd/amdk8/early_ht.c"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/k8/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/p6/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
+#include "northbridge/amd/amdk8/debug.c" 
 #include "northbridge/amd/amdk8/cpu_rev.c"
- 
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c" 
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
+static void hard_reset(void)
+{
+        set_bios_reset();
+        
+        /* enable cf9 */
+        pci_write_config8(PCI_DEV(0, 0x02, 3), 0x41, 0xf1);
+        /* reset */
+        outb(0x0e, 0x0cf9);
+}
 
+static void soft_reset(void)
+{
+        set_bios_reset();
+        pci_write_config8(PCI_DEV(0, 0x02, 0), 0x47, 1);
+}
+ 
 #define REV_B_RESET 0
 static void memreset_setup(void)
 {
-#if REV_B_RESET==1
+   if (is_cpu_pre_c0()) {
         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
-#else
+   }
+   else {
         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
-#endif
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); 
+   }
+        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
 }
 
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
+   if (is_cpu_pre_c0()) {
         udelay(800);
-#if REV_B_RESET==1
         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
-#endif
         udelay(90);
+   }
 }
 
+
 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
 {
+	/* Routing Table Node i 
+	 *
+	 * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c 
+	 *  i:    0,    1,    2,    3,    4,    5,    6,    7
+	 *
+	 * [ 0: 3] Request Route
+	 *     [0] Route to this node
+	 *     [1] Route to Link 0
+	 *     [2] Route to Link 1
+	 *     [3] Route to Link 2
+	 * [11: 8] Response Route
+	 *     [0] Route to this node
+	 *     [1] Route to Link 0
+	 *     [2] Route to Link 1
+	 *     [3] Route to Link 2
+	 * [19:16] Broadcast route
+	 *     [0] Route to this node
+	 *     [1] Route to Link 0
+	 *     [2] Route to Link 1
+	 *     [3] Route to Link 2
+	 */
+
 	uint32_t ret=0x00010101; /* default row entry */
 
+
 	return ret;
 }
 
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+        /* nothing to do */
+}
+ 
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);
 }
 
-/* include mainboard specific ht code */
-#include "hypertransport.c"
-
-//#include "northbridge/amd/amdk8/cpu_ldtstop.c"
-//#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
-
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "sdram/generic_sdram.c"
 
-static void enable_lapic(void)
-{
-	msr_t msr;
-	msr = rdmsr(0x1b);
-	msr.hi &= 0xffffff00;
-	msr.lo &= 0x000007ff;
-	msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
-	wrmsr(0x1b, msr);
-}
-
-static void stop_this_cpu(void)
-{
-	unsigned apicid;
-	apicid = apic_read(APIC_ID) >> 24;
-
-	/* Send an APIC INIT to myself */
-	apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
-	apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
-	/* Wait for the ipi send to finish */
-	apic_wait_icr_idle();
-
-	/* Deassert the APIC INIT */
-	apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
-	apic_write(APIC_ICR,  APIC_INT_LEVELTRIG | APIC_DM_INIT);
-	/* Wait for the ipi send to finish */
-	apic_wait_icr_idle();
-
-	/* If I haven't halted spin forever */
-	for(;;) {
-		hlt();
-	}
-}
-#define FIRST_CPU  1
-#define SECOND_CPU 0
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 static void main(void)
 {
+	/*
+	 * GPIO28 of 8111 will control H0_MEMRESET_L
+	 * GPIO29 of 8111 will control H1_MEMRESET_L
+	 */
 	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
 		{
 			.node_id = 0,
 			.f0 = PCI_DEV(0, 0x18, 0),
@@ -108,42 +121,37 @@ static void main(void)
 			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 		},
-#endif
-#if SECOND_CPU
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
-#endif
 	};
-	if (cpu_init_detected()) {
-		asm("jmp __cpu_reset");
-	}
-	enable_lapic();
-	init_timer();
-	if (!boot_cpu() ) {
-		notify_bsp_ap_is_stopped();
-		stop_this_cpu();
-	}
-	uart_init();
-	console_init();
-	setup_default_resource_map();
-	setup_coherent_ht_domain();
-	enumerate_ht_chain(0);
-	distinguish_cpu_resets(0);
-	
+        
+	int needs_reset;
+        enable_lapic();
+        init_timer();
+        if (cpu_init_detected()) {
+                asm("jmp __cpu_reset");
+        }
+        distinguish_cpu_resets();
+        if (!boot_cpu()) {
+                stop_this_cpu();
+        }
+        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+        uart_init();
+        console_init();
+        setup_default_resource_map();
+        needs_reset = setup_coherent_ht_domain();
+        needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
+        if (needs_reset) {
+                print_info("ht reset -\r\n");
+                soft_reset();
+        }	
 #if 0
 	print_pci_devices();
 #endif
 	enable_smbus();
 #if 0
-	dump_spd_registers(&cpu[0]);
+//	dump_spd_registers(&cpu[0]);
+	dump_smbus_registers();
 #endif
+
 	memreset_setup();
 	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 
diff --git a/src/mainboard/tyan/s2850/cmos.layout b/src/mainboard/tyan/s2850/cmos.layout
index 5ba4c032c1..247715e6ac 100644
--- a/src/mainboard/tyan/s2850/cmos.layout
+++ b/src/mainboard/tyan/s2850/cmos.layout
@@ -29,6 +29,9 @@ entries
 386          1       e       1        ECC_memory
 388          4       r       0        reboot_bits
 392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
@@ -36,7 +39,14 @@ entries
 424          4       e       7        boot_third
 428          4       h       0        boot_index
 432	     8       h       0        boot_countdown
-1008         16      h       0        check_sum
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        reserved_memory
+
+
 
 enumerations
 
@@ -66,9 +76,21 @@ enumerations
 7     9     Fallback_HDD
 7     10    Fallback_Floppy
 #7     3     ROM
+8     0     200Mhz
+8     1     166Mhz
+8     2     133Mhz
+8     3     100Mhz
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
 
 checksums
 
-checksum 392 1007 1008
+checksum 392 983 984
 
 
diff --git a/src/mainboard/tyan/s2850/failover.c b/src/mainboard/tyan/s2850/failover.c
index 8eeeaef7e1..b22abfea06 100644
--- a/src/mainboard/tyan/s2850/failover.c
+++ b/src/mainboard/tyan/s2850/failover.c
@@ -3,36 +3,78 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
-#include "arch/romcc_io.h"
+#include <arch/romcc_io.h>
+#include <arch/smp/lapic.h>
 #include "pc80/mc146818rtc_early.c"
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 #include "cpu/p6/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 
+#define HAVE_REGPARM_SUPPORT 0
+#if HAVE_REGPARM_SUPPORT
+static unsigned long main(unsigned long bist)
+{
+#else
 static void main(void)
 {
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain(0);
+	unsigned long bist = 0;
+#endif
+	/* Make cerain my local apic is useable */
+	enable_lapic();
 
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a cpu reset? */
+	/* Is this a cpu only reset? */
 	if (cpu_init_detected()) {
 		if (last_boot_normal()) {
-			asm("jmp __normal_image");
+			goto normal_image;
 		} else {
-			asm("jmp __cpu_reset");
+			goto cpu_reset;
 		}
 	}
 	/* Is this a secondary cpu? */
-	else if (!boot_cpu() && last_boot_normal()) {
-		asm("jmp __normal_image");
+	if (!boot_cpu()) {
+		if (last_boot_normal()) {
+			goto normal_image;
+		} else {
+			goto fallback_image;
+		}
+	}
+	
+
+	/* Nothing special needs to be done to find bus 0 */
+	/* Allow the HT devices to be found */
+	enumerate_ht_chain();
+	
+	/* Setup the 8111 */
+	amd8111_enable_rom();
+
+	/* Is this a deliberate reset by the bios */
+	if (bios_reset_detected() && last_boot_normal()) {
+		goto normal_image;
 	}
 	/* This is the primary cpu how should I boot? */
 	else if (do_normal_boot()) {
-		asm("jmp __normal_image");
+		goto normal_image;
+	}
+	else {
+		goto fallback_image;
 	}
+ normal_image:
+	asm("jmp __normal_image" 
+		: /* outputs */ 
+		: "a" (bist) /* inputs */
+		: /* clobbers */
+		);
+ cpu_reset:
+	asm("jmp __cpu_reset"
+		: /* outputs */ 
+		: "a"(bist) /* inputs */
+		: /* clobbers */
+		);
+ fallback_image:
+#if HAVE_REGPARM_SUPPORT
+	return bist;
+#else
+	return;
+#endif
 }
diff --git a/src/mainboard/tyan/s2850/irq_tables.c b/src/mainboard/tyan/s2850/irq_tables.c
index 3f1e5bdf24..f0bcd77c8c 100644
--- a/src/mainboard/tyan/s2850/irq_tables.c
+++ b/src/mainboard/tyan/s2850/irq_tables.c
@@ -22,15 +22,15 @@ const struct irq_routing_table intel_irq_routing_table = {
 	{
 		{1,(2<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
 		{0x2,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},
-		{0x2,0x68, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
-		{0x2,0x58, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
-		{0x2,0x18, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
-		{0x2,0x30, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x1, 0},
-		{0x2,0x38, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x2, 0},
-		{0x2,0x40, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
-		{0x2,0x48, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x4, 0},
-		{0x2,0x50, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x5, 0},
-		{0x2,0x70, {{0x1, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
-		{0x2,0x60, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
+		{0x2,(0x0d<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
+		{0x2,(0x0b<<3)|0, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
+		{0x2,(3<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
+		{0x2,(6<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x1, 0},
+		{0x2,(7<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x2, 0},
+		{0x2,(8<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
+		{0x2,(9<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x4, 0},
+		{0x2,(0x0a<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x6, 0},
+		{0x2,(0x0e<<3)|0, {{0x1, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
+		{0x2,(0x0c<<3)|0, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
 	}
 };
diff --git a/src/mainboard/tyan/s2850/mainboard.c b/src/mainboard/tyan/s2850/mainboard.c
index 11ed302083..6864a0333d 100644
--- a/src/mainboard/tyan/s2850/mainboard.c
+++ b/src/mainboard/tyan/s2850/mainboard.c
@@ -38,7 +38,7 @@ static void fixup_lsi_53c1030(struct device *pdev)
 }
 #endif
 //extern static void lsi_scsi_init(struct device *dev);
-#if 1
+#if 0
 static void print_pci_regs(struct device *dev)
 {
       uint8_t byte;
@@ -120,7 +120,7 @@ static void onboard_scsi_fixup(void)
 //	print_mem();
 //	amd8111_enable_rom();
 }
-#if 1
+#if 0
 static void vga_fixup(void) {
         // we do this right here because:
         // - all the hardware is working, and some VGA bioses seem to need
@@ -154,8 +154,8 @@ enable(struct chip *chip, enum chip_pass pass)
                 case CONF_PASS_PRE_BOOT:
 			if (conf->fixup_scsi)
         			onboard_scsi_fixup();
-			if (conf->fixup_vga)
-				vga_fixup();
+//			if (conf->fixup_vga)
+//				vga_fixup();
 			printk_debug("mainboard fixup pass %d done\r\n",
 					pass);
 			break;
diff --git a/src/mainboard/tyan/s2850/mptable.c b/src/mainboard/tyan/s2850/mptable.c
index 77cf102904..6c457808c1 100644
--- a/src/mainboard/tyan/s2850/mptable.c
+++ b/src/mainboard/tyan/s2850/mptable.c
@@ -11,6 +11,10 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
         static const char productid[12] = "S2850       ";
         struct mp_config_table *mc;
 
+        unsigned char bus_num;
+        unsigned char bus_isa;
+        unsigned char bus_8111_1;
+
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
         memset(mc, 0, sizeof(*mc));
 
@@ -29,43 +33,107 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
         mc->reserved = 0;
 
         smp_write_processors(mc, processor_map);
+        {
+                device_t dev;
+
+                /* 8111 */
+                dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
+                if (dev) {
+                        bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+                        bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+                        bus_isa++;
+                }     
+                else {  
+                        printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
+
+                        bus_8111_1 = 2;
+                        bus_isa = 3;
+                }
+        }
+/*Bus:          Bus ID  Type*/
+        /* define bus and isa numbers */
+        for(bus_num = 0; bus_num < bus_isa; bus_num++) {
+                smp_write_bus(mc, bus_num, "PCI   ");
+        }
+        smp_write_bus(mc, bus_isa, "ISA   ");
 
 
-/*Bus:		Bus ID	Type*/
-	smp_write_bus(mc, 0, "PCI   ");
-	smp_write_bus(mc, 1, "PCI   ");
-	smp_write_bus(mc, 2, "PCI   ");
-	smp_write_bus(mc, 3, "ISA   ");
-	
 /*I/O APICs:	APIC ID	Version	State		Address*/
 	smp_write_ioapic(mc, 1, 0x11, 0xfec00000);
   
-/*I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#
-*/	
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x1, 0x1, 0x1);
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x0, 0x1, 0x2);
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x3, 0x1, 0x3);
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x4, 0x1, 0x4);
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x5, 0x1, 0x5);
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x6, 0x1, 0x6);
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x7, 0x1, 0x7);
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x8, 0x1, 0x8);
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xc, 0x1, 0xc);
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xd, 0x1, 0xd);
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xe, 0x1, 0xe);
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xf, 0x1, 0xf);
- 
+/*I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
+
+        smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x1, 0x0);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, 0x1, 0x1);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x1, 0x2);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, 0x1, 0x3);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, 0x1, 0x4);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, 0x1, 0x6);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, 0x1, 0x7);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, 0x1, 0x8);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, 0x1, 0xc);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, 0x1, 0xd);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, 0x1, 0xe);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, 0x1, 0xf);
+
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (2<<2)|3, 0x1, 0x13);
 	
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (2<<2)|3, 0x1, 0x13);
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x3, 0x1, 0x13);
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x34, 0x1, 0x13);
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x2c, 0x1, 0x12);
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x38, 0x1, 0x10);
+//On Board AMD USB
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, 0x1, 0x13);
+
+//On Board ATI Display Adapter
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|0, 0x1, 0x12);
+
+//Onboard Broadcom 5705 NIC
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0d<<2)|0, 0x1, 0x13);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0e<<2)|0, 0x1, 0x10);
+//Onboard SI Serial ATA
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0c<<2)|0, 0x1, 0x11);
+
+
+//PCI Slot 1
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x03<<2)|0, 0x1, 0x10);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x03<<2)|1, 0x1, 0x11);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x03<<2)|2, 0x1, 0x12);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x03<<2)|3, 0x1, 0x13);
+
+
+//PCI Slot 2
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|0, 0x1, 0x11);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|1, 0x1, 0x12);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|2, 0x1, 0x13);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|3, 0x1, 0x10);
+
+
+//PCI Slot 3
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x07<<2)|0, 0x1, 0x12);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x07<<2)|1, 0x1, 0x13);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x07<<2)|2, 0x1, 0x10);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x07<<2)|3, 0x1, 0x11);
+
+
+//PCI Slot 4
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|0, 0x1, 0x13);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|1, 0x1, 0x10);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|2, 0x1, 0x11);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|3, 0x1, 0x12);
+
+//PCI Slot 5
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|0, 0x1, 0x10);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|1, 0x1, 0x11);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|2, 0x1, 0x12);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|3, 0x1, 0x13);
 
+//PCI Slot 6
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|0, 0x1, 0x11);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|1, 0x1, 0x12);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|2, 0x1, 0x13);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|3, 0x1, 0x10);
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x1);
+        smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
+        smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
 	/* There is no extension information... */
 
 	/* Compute the checksums */