diff options
| author | Eric Biederman <ebiederm@xmission.com> | 2004-10-23 02:47:13 +0000 |
|---|---|---|
| committer | Eric Biederman <ebiederm@xmission.com> | 2004-10-23 02:47:13 +0000 |
| commit | 60216355d21fae62daf00afa66443b03ed743e2a (patch) | |
| tree | 18e3eb1ba2abbac7cc2e49803354ee1a1303e060 /src/mainboard/tyan/s2735 | |
| parent | 720a8f57ef1a1a4264354dd9601c53e12b82ae36 (diff) | |
- With Xeon cpus it seems best to use the tsc calibrated with timer2 as
the time source. The apic timer also has a variable time base.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2735')
| -rw-r--r-- | src/mainboard/tyan/s2735/Options.lb | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/tyan/s2735/Options.lb b/src/mainboard/tyan/s2735/Options.lb index cecb58bb9f..c68fd37489 100644 --- a/src/mainboard/tyan/s2735/Options.lb +++ b/src/mainboard/tyan/s2735/Options.lb @@ -79,6 +79,12 @@ default HAVE_HARD_RESET=1 #default HARD_RESET_FUNCTION=0 ## +## Delay timer options +## +default CONFIG_UDELAY_TSC=1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + +## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 |