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authorStefan Reinauer <stepan@openbios.org>2004-08-07 19:58:46 +0000
committerStefan Reinauer <stepan@openbios.org>2004-08-07 19:58:46 +0000
commit198409afe08df8285f80327307670e9d859c9e2b (patch)
tree714e5c8f5df053f7cef54b1f3a4ff7c91c90d4b9 /src/mainboard/technologic/ts5300/failover.c
parent40ab2d1213f65bb540cc6b5ddc1794c0d4db38f1 (diff)
create some technologic systems ts530 infrastructure
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/technologic/ts5300/failover.c')
-rw-r--r--src/mainboard/technologic/ts5300/failover.c29
1 files changed, 29 insertions, 0 deletions
diff --git a/src/mainboard/technologic/ts5300/failover.c b/src/mainboard/technologic/ts5300/failover.c
new file mode 100644
index 0000000000..bd0df4e89d
--- /dev/null
+++ b/src/mainboard/technologic/ts5300/failover.c
@@ -0,0 +1,29 @@
+#define ASSEMBLY 1
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include "arch/romcc_io.h"
+#include "pc80/mc146818rtc_early.c"
+#include "cpu/p6/boot_cpu.c"
+
+static void main(void)
+{
+ /* for now, just always assume failure */
+
+#if 0
+ /* Is this a cpu reset? */
+ if (cpu_init_detected()) {
+ if (last_boot_normal()) {
+ asm("jmp __normal_image");
+ } else {
+ asm("jmp __cpu_reset");
+ }
+ }
+
+ /* This is the primary cpu how should I boot? */
+ else if (do_normal_boot()) {
+ asm("jmp __normal_image");
+ }
+#endif
+}