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| author | Angel Pons <th3fanbus@gmail.com> | 2021-09-08 15:06:56 +0200 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@gmail.com> | 2024-04-16 01:46:05 +0000 |
| commit | 6ef23316c235d14213d0bdc48c6853d3059a0b64 (patch) | |
| tree | 75e69d6b500ef33f32eaff750eb24c6f0496782e /src/mainboard/system76/tgl-u | |
| parent | fd46b497ead843eccfd80124ca8fbba7e57a3631 (diff) | |
sb/intel/lynxpoint/pcie.c: Fix 0xf5 register mask
Lynx Point PCH reference code version 1.9.1 masks the upper 4 bits of
the PCIe root port register at offset 0xf5.
Change-Id: I9529ad88d34a5cb4a09843e3165f3a70c5ea22e8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57502
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/system76/tgl-u')
0 files changed, 0 insertions, 0 deletions