diff options
| author | Tim Crawford <tcrawford@system76.com> | 2022-12-30 10:05:38 -0700 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-01-05 17:55:17 +0000 |
| commit | 7c92712cf0fdfd85fa518cda57e19d1cd7097108 (patch) | |
| tree | 0faf94fe1f786c953c4a9dd5cb7f982963d875b2 /src/mainboard/system76/tgl-u/variants/darp7 | |
| parent | 06545e0744e322b2148f4cb52eb976737754e65b (diff) | |
mb/system76/tgl-u: Add FSP-S configs per variant
Configure CPU PCIe RP and IOM per variant.
Change-Id: I9c38af42206497dbb9436e9f2b8aff46fa4d3fb9
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Diffstat (limited to 'src/mainboard/system76/tgl-u/variants/darp7')
| -rw-r--r-- | src/mainboard/system76/tgl-u/variants/darp7/ramstage.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c b/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c new file mode 100644 index 0000000000..a60587d5d4 --- /dev/null +++ b/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + // Disable AER to fix suspend failing with some SSDs. + params->CpuPcieRpAdvancedErrorReporting[0] = 0; + params->CpuPcieRpLtrEnable[0] = 1; + params->CpuPcieRpPtmEnabled[0] = 0; + + // IOM config + params->PchUsbOverCurrentEnable = 0; + params->PortResetMessageEnable[5] = 1; // J_TYPEC2 +} |