soc/intel/tigerlake: Drop redundant PcieRpEnable

The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.

Thanks to Nicholas for doing all the mainboard legwork!

Change-Id: Iacfef5f032278919f1fcf49e31fa42bcbf1eaf20
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79920
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 0 insertions, 4 deletions

diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb
index b463fe7b7b..bfbc5c5090 100644
--- a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb
@@ -53,21 +53,18 @@ chip soc/intel/tigerlake
 		end
 		device ref pcie_rp5 on
 			# PCIe root port #5 x1, Clock 8 (GLAN)
-			register "PcieRpEnable[4]" = "1"
 			register "PcieRpLtrEnable[4]" = "1"
 			#register "PcieClkSrcUsage[8]" = "4"
 			register "PcieClkSrcClkReq[8]" = "8"
 		end
 		device ref pcie_rp7 on
 			# PCIe root port #7 x1, Clock 3 (CARD)
-			register "PcieRpEnable[6]" = "1"
 			register "PcieRpLtrEnable[6]" = "1"
 			register "PcieClkSrcUsage[3]" = "6"
 			register "PcieClkSrcClkReq[3]" = "3"
 		end
 		device ref pcie_rp8 on
 			# PCIe root port #8 x1, Clock 2 (WLAN)
-			register "PcieRpEnable[7]" = "1"
 			register "PcieRpLtrEnable[7]" = "1"
 			register "PcieClkSrcUsage[2]" = "7"
 			register "PcieClkSrcClkReq[2]" = "2"
@@ -75,7 +72,6 @@ chip soc/intel/tigerlake
 		end
 		device ref pcie_rp9 on
 			# PCIe root port #9 x4, Clock 10 (SSD2)
-			register "PcieRpEnable[8]" = "1"
 			register "PcieRpLtrEnable[8]" = "1"
 			register "PcieClkSrcUsage[10]" = "8"
 			register "PcieClkSrcClkReq[10]" = "10"