mb/system76/rpl: Add Gazelle 18

The Gazelle 18 (gaze18) is a Raptor Lake-H board.

Tested with a custom TianoCore UefiPayloadPkg.

Working:

- PS/2 keyboard
- I2C HID touchpad
- Both DIMM slots
- M.2 NVMe SSD slot
- M.2 SATA SSD slot
- All USB ports
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined headphone + mic 3.5mm audio
- 3.5mm microphone input
- S3 suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.2.6

Not working:

- Discrete/Hybrid graphics

Change-Id: I4599bf12c0f3048f9328f336cc8971400f5fd1a0
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>

8 files changed, 404 insertions, 0 deletions

diff --git a/src/mainboard/system76/rpl/variants/gaze18/board.fmd b/src/mainboard/system76/rpl/variants/gaze18/board.fmd
new file mode 100644
index 0000000000..fdf1ebdf52
--- /dev/null
+++ b/src/mainboard/system76/rpl/variants/gaze18/board.fmd
@@ -0,0 +1,12 @@
+FLASH 32M {
+	SI_DESC 4K
+	SI_ME 4824K
+	SI_BIOS@16M 16M {
+		RW_MRC_CACHE 64K
+		SMMSTORE(PRESERVE) 256K
+		WP_RO {
+			FMAP 4K
+			COREBOOT(CBFS)
+		}
+	}
+}
diff --git a/src/mainboard/system76/rpl/variants/gaze18/board_info.txt b/src/mainboard/system76/rpl/variants/gaze18/board_info.txt
new file mode 100644
index 0000000000..c8e58d6fb2
--- /dev/null
+++ b/src/mainboard/system76/rpl/variants/gaze18/board_info.txt
@@ -0,0 +1,2 @@
+Board name: gaze18
+Release year: 2023
diff --git a/src/mainboard/system76/rpl/variants/gaze18/data.vbt b/src/mainboard/system76/rpl/variants/gaze18/data.vbt
new file mode 100644
index 0000000000..a43a61ce86
--- /dev/null
+++ b/src/mainboard/system76/rpl/variants/gaze18/data.vbt
diff --git a/src/mainboard/system76/rpl/variants/gaze18/gpio.c b/src/mainboard/system76/rpl/variants/gaze18/gpio.c
new file mode 100644
index 0000000000..1f603fc966
--- /dev/null
+++ b/src/mainboard/system76/rpl/variants/gaze18/gpio.c
@@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
+	PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), // LAN_WAKEUP#
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
+	PAD_NC(GPD7, NONE),
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // Not documented
+	PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
+	PAD_NC(GPD11, NONE),
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
+	PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0#
+	PAD_NC(GPP_A6, NONE),
+	PAD_NC(GPP_A7, NONE),
+	PAD_CFG_GPO(GPP_A8, 1, PLTRST), // SATA_PWR_EN
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET_N
+	PAD_NC(GPP_A11, NONE),
+	PAD_NC(GPP_A12, NONE),
+	PAD_CFG_GPO(GPP_A13, 1, PLTRST), // BT_EN
+	// GPP_A14 (DGPU_PWR_EN) configured in bootblock
+	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF2), // MDP_B_HPD
+	PAD_NC(GPP_A16, NONE), // USB_OC3#
+	PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN#
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD
+	PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R
+	PAD_CFG_GPO(GPP_A20, 0, DEEP), // PEX_WAKE#
+	PAD_NC(GPP_A21, NONE),
+	PAD_NC(GPP_A22, NONE),
+	PAD_NC(GPP_A23, NONE),
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
+	// GPP_B2 (DGPU_RST#_PCH) configured in bootblock
+	PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
+	PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI#
+	PAD_NC(GPP_B5, NONE),
+	PAD_NC(GPP_B6, NONE),
+	PAD_NC(GPP_B7, NONE),
+	PAD_NC(GPP_B8, NONE),
+	// GPP_B9 missing
+	// GPP_B10 missing
+	PAD_NC(GPP_B11, NONE),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // BUF_PLT_RST#
+	PAD_NC(GPP_B14, NONE), // TOP SWAP OVERRIDE strap
+	PAD_NC(GPP_B15, NONE),
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_NC(GPP_B18, NONE), // NO REBOOT strap
+	// GPP_B19 missing
+	// GPP_B20 missing
+	// GPP_B21 missing
+	// GPP_B22 missing
+	PAD_NC(GPP_B23, NONE), // CPUNSSC CLOCK FREQ strap
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST), // M2_PWR_EN2
+	PAD_NC(GPP_C3, NONE),
+	PAD_NC(GPP_C4, NONE),
+	PAD_NC(GPP_C5, NONE), // TLS CONFIDENTIALITY strap
+	PAD_NC(GPP_C6, NONE),
+	PAD_NC(GPP_C7, NONE),
+	// GPP_C8 missing
+	// GPP_C9 missing
+	// GPP_C10 missing
+	// GPP_C11 missing
+	// GPP_C12 missing
+	// GPP_C13 missing
+	// GPP_C14 missing
+	// GPP_C15 missing
+	// GPP_C16 missing
+	// GPP_C17 missing
+	// GPP_C18 missing
+	// GPP_C19 missing
+	// GPP_C20 missing
+	// GPP_C21 missing
+	// GPP_C22 missing
+	// GPP_C23 missing
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
+	PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
+	PAD_NC(GPP_D2, NONE),
+	PAD_NC(GPP_D3, NONE),
+	PAD_CFG_GPI(GPP_D4, NONE, DEEP), // GPIO_LAN_EN
+	// GPP_D5 (SSD0_CLKREQ#) configured by FSP
+	// GPP_D6 (SSD1_CLKREQ#) configured by FSP
+	// GPP_D7 (WLAN_CLKREQ#) configured by FSP
+	// GPP_D8 (GPU_PCIE_CLKREQ#) configured by FSP
+	PAD_NC(GPP_D9, NONE),
+	PAD_NC(GPP_D10, NONE),
+	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF2), // I_MDP_CLK
+	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF2), // I_MDP_DATA
+	PAD_NC(GPP_D13, NONE),
+	PAD_CFG_GPO(GPP_D14, 1, PLTRST), // M2_PWR_EN1
+	PAD_CFG_GPO(GPP_D15, 0, DEEP), // LANRTD3_WAKE#
+	PAD_CFG_GPO(GPP_D16, 1, PLTRST), // LAN_RTD3_EN#
+	PAD_NC(GPP_D17, NONE),
+	PAD_NC(GPP_D18, NONE),
+	PAD_NC(GPP_D19, NONE),
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
+	_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
+	PAD_NC(GPP_E2, NONE), // BOARD_ID2
+	PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN
+	PAD_NC(GPP_E4, NONE),
+	PAD_NC(GPP_E5, NONE),
+	PAD_NC(GPP_E6, NONE), // JTAG ODT DISABLE strap
+	PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
+	PAD_CFG_GPO(GPP_E8, 0, DEEP), // SLP_DRAM#
+	PAD_NC(GPP_E9, NONE), // USB_OC0#
+	PAD_CFG_GPO(GPP_E10, 0, DEEP), // KBLED_DET
+	PAD_NC(GPP_E11, NONE), // BOARD_ID1
+	PAD_NC(GPP_E12, NONE),
+	PAD_NC(GPP_E13, NONE), // BOARD_ID4
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_E15, 0, DEEP),
+	PAD_CFG_GPO(GPP_E16, 0, DEEP),
+	PAD_NC(GPP_E17, NONE), // BOARD_ID3
+	PAD_NC(GPP_E18, NONE),
+	PAD_NC(GPP_E19, NONE), // strap
+	PAD_NC(GPP_E20, NONE),
+	PAD_NC(GPP_E21, NONE), // strap
+	PAD_NC(GPP_E22, NONE),
+	PAD_NC(GPP_E23, NONE),
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
+	// GPP_F5 (CNVI_CLKREQ) configured by FSP
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_NC(GPP_F7, NONE), // MCRO LDO BYPASS strap
+	// GPP_F8 missing
+	PAD_NC(GPP_F9, NONE),
+	PAD_CFG_GPO(GPP_F10, 0, DEEP), // PCIE_GLAN_RST#
+	PAD_NC(GPP_F11, NONE),
+	PAD_CFG_GPI(GPP_F12, NONE, PLTRST), // GPIO4_GC6_NVVDD_EN_R
+	PAD_CFG_GPI(GPP_F13, NONE, PLTRST), // GC6_FB_EN_PCH
+	PAD_NC(GPP_F14, NONE), // LIGHT_KB_DET#
+	PAD_NC(GPP_F15, NONE),
+	PAD_CFG_GPO(GPP_F16, 0, DEEP), // GPU_EVENT#
+	PAD_NC(GPP_F17, NONE),
+	PAD_CFG_GPO(GPP_F18, 0, DEEP), // DGPU_OVRM
+	// GPP_F19 (GLAN_CLKREQ#) configured by FSP
+	PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M.2_PLT_RST_CNTRL1#
+	PAD_NC(GPP_F21, NONE),
+	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), // VNN_CTRL
+	PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), // V1P05_CTRL
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_NC(GPP_H0, NONE),
+	PAD_CFG_GPO(GPP_H1, 0, DEEP), // M.2_PLT_RST_CNTRL2#
+	PAD_CFG_GPO(GPP_H2, 0, DEEP), // M.2_PLT_RST_CNTRL3#
+	PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP
+	PAD_NC(GPP_H6, NONE),
+	PAD_NC(GPP_H7, NONE),
+	PAD_CFG_GPO(GPP_H8, 0, DEEP), // CNVI_MFUART2_RXD
+	PAD_CFG_GPO(GPP_H9, 0, DEEP), // CNVI_MFUART2_TXD
+	// GPP_H10 (UART0_RX) configured in bootblock
+	// GPP_H11 (UART0_TX) configured in bootblock
+	PAD_NC(GPP_H12, NONE),
+	_PAD_CFG_STRUCT(GPP_H13, 0x04001500, 0x0000), // DEVSLP1
+	// GPP_H14 missing
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), // HDMI_CTRLCLK
+	// GPP_H16 missing
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // HDMI_CTRLDATA
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
+	PAD_NC(GPP_H19, NONE),
+	PAD_NC(GPP_H20, NONE),
+	PAD_NC(GPP_H21, NONE),
+	PAD_NC(GPP_H22, NONE),
+	// GPP_H23 (CARD_CLKREQ#) configured by FSP
+
+	/* ------- GPIO Group GPP_R ------- */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT / ME_WE
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // AZ_RST#_R
+	PAD_NC(GPP_R5, NONE),
+	PAD_NC(GPP_R6, NONE),
+	PAD_NC(GPP_R7, NONE),
+
+	/* ------- GPIO Group GPP_S ------- */
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+	PAD_NC(GPP_S6, NONE),
+	PAD_NC(GPP_S7, NONE),
+
+	/* ------- GPIO Group GPP_T ------- */
+	PAD_NC(GPP_T2, NONE),
+	PAD_NC(GPP_T3, NONE),
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/system76/rpl/variants/gaze18/gpio_early.c b/src/mainboard/system76/rpl/variants/gaze18/gpio_early.c
new file mode 100644
index 0000000000..85b9307d45
--- /dev/null
+++ b/src/mainboard/system76/rpl/variants/gaze18/gpio_early.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
+	PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/system76/rpl/variants/gaze18/hda_verb.c b/src/mainboard/system76/rpl/variants/gaze18/hda_verb.c
new file mode 100644
index 0000000000..82f047d238
--- /dev/null
+++ b/src/mainboard/system76/rpl/variants/gaze18/hda_verb.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC256 */
+	0x10ec0256, /* Vendor ID */
+	0x15585630, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15585630),
+	AZALIA_RESET(1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x02a11040),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x02211020),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/system76/rpl/variants/gaze18/overridetree.cb b/src/mainboard/system76/rpl/variants/gaze18/overridetree.cb
new file mode 100644
index 0000000000..029760f756
--- /dev/null
+++ b/src/mainboard/system76/rpl/variants/gaze18/overridetree.cb
@@ -0,0 +1,92 @@
+chip soc/intel/alderlake
+	device domain 0 on
+		subsystemid 0x1558 0x5630 inherit
+
+		device ref xhci on
+			# USB2
+			register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_TYPEC1 (USB 3.1 Gen2)
+			register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A (USB 3.1 Gen2)
+			register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # J_TYPEC2 (USB 3.1 Gen2)
+			register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Finger
+			register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+			register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A (USB 3.1 Gen2)
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC2
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1
+			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1
+		end
+
+		device ref i2c0 on
+			# Touchpad I2C bus
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN0412""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""FTCS1000""
+				register "generic.desc" = ""FocalTech Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 38 on end
+			end
+		end
+
+		device ref pcie5_0 on
+			# CPU PCIe RP#2 x8, Clock 3 (GPU)
+			register "cpu_pcie_rp[CPU_RP(2)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+		device ref pcie4_0 on
+			# CPU RP#1 x4, Clock 0 (SSD0)
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_src = 0,
+				.clk_req = 0,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+		device ref pcie_rp5 on
+			# PCH RP#5 x4, Clock 1 (SSD1)
+			register "pch_pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 1,
+				.clk_req = 1,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+		device ref pcie_rp9 on
+			# PCH RP#9 x1, Clock 6 (GLAN)
+			register "pch_pcie_rp[PCH_RP(9)]" = "{
+				.clk_src = 6,
+				.clk_req = 6,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			device pci 00.0 on end
+		end
+		device ref pcie_rp10 on
+			# PCH RP#10 x1, Clock 2 (WLAN)
+			register "pch_pcie_rp[PCH_RP(10)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+		device ref pcie_rp11 on
+			# PCH RP#11 x1, Clock 5 (CARD)
+			register "pch_pcie_rp[PCH_RP(11)]" = "{
+				.clk_src = 5,
+				.clk_req = 5,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+	end
+end
diff --git a/src/mainboard/system76/rpl/variants/gaze18/romstage.c b/src/mainboard/system76/rpl/variants/gaze18/romstage.c
new file mode 100644
index 0000000000..1e597c72a6
--- /dev/null
+++ b/src/mainboard/system76/rpl/variants/gaze18/romstage.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg board_cfg = {
+		.type = MEM_TYPE_DDR5,
+		.ect = true,
+		.LpDdrDqDqsReTraining = 1,
+	};
+	const struct mem_spd spd_info = {
+		.topo = MEM_TOPO_DIMM_MODULE,
+		.smbus = {
+			[0] = { .addr_dimm[0] = 0x50, },
+			[1] = { .addr_dimm[0] = 0x52, },
+		},
+	};
+	const bool half_populated = false;
+
+	// Set primary display to internal graphics
+	mupd->FspmConfig.PrimaryDisplay = 0;
+
+	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+	mupd->FspmConfig.GpioOverride = 0;
+
+	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
+}