diff options
| author | Felix Singer <felixsinger@posteo.net> | 2023-10-26 16:14:34 +0200 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2023-10-30 14:00:59 +0000 |
| commit | 983b169a366a3db03c9fab989e36973b5a6eee96 (patch) | |
| tree | ca402e7b71be912882efe8466216085157341bbe /src/mainboard/system76/rpl/variants/addw3/overridetree.cb | |
| parent | ee1fd54aef8ec0aba9e3dc01111251e1ae6b9d12 (diff) | |
mb/system76/rpl/dt: Use comma separated list for arrays
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.
Don't convert the settings for PCIe root ports as they should stay in
the device scope of them.
While on it, remove superfluous comments related to modified lines.
Change-Id: I15f326774850b3c9562f7eebb78f29430dec1031
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78667
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/system76/rpl/variants/addw3/overridetree.cb')
| -rw-r--r-- | src/mainboard/system76/rpl/variants/addw3/overridetree.cb | 27 |
1 files changed, 15 insertions, 12 deletions
diff --git a/src/mainboard/system76/rpl/variants/addw3/overridetree.cb b/src/mainboard/system76/rpl/variants/addw3/overridetree.cb index cddc3dd67c..292673a2ca 100644 --- a/src/mainboard/system76/rpl/variants/addw3/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/addw3/overridetree.cb @@ -8,18 +8,21 @@ chip soc/intel/alderlake #TODO: DDIB and DDID are both connected to TBT device ref xhci on - # USB2 - register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A 3.2 Gen 1 (Left) - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A 2.0 (Left) - # Port reset messaging cannot be used, so do not use USB2_PORT_TYPE_C for these - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-C 3.2 Gen 2 (Rear) - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Thunderbolt (Right) - register "usb2_ports[10]" = "USB2_PORT_MID(OC_SKIP)" # Camera - register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # Secure Pad - register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - # USB3 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A 3.2 Gen 1 (Left) - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C 3.2 Gen 2 (Rear) + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), /* Type-A 3.2 Gen 1 (Left) */ + [1] = USB2_PORT_MID(OC_SKIP), /* Type-A 2.0 (Left) */ + /* Port reset messaging cannot be used, + * so do not use USB2_PORT_TYPE_C for these */ + [2] = USB2_PORT_MID(OC_SKIP), /* Type-C 3.2 Gen 2 (Rear) */ + [8] = USB2_PORT_MID(OC_SKIP), /* Type-C Thunderbolt (Right) */ + [10] = USB2_PORT_MID(OC_SKIP), /* Camera */ + [11] = USB2_PORT_MID(OC_SKIP), /* Secure Pad */ + [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */ + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A 3.2 Gen 1 (Left) */ + [2] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C 3.2 Gen 2 (Rear) */ + }" end device ref i2c0 on |