diff options
| author | Felix Singer <felixsinger@posteo.net> | 2023-10-26 15:02:46 +0200 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2023-10-30 14:00:37 +0000 |
| commit | d163253ba047515e3317e9da38aa7cc5714a7f0c (patch) | |
| tree | 0c0c7148194fb268d1ed23159df08f444c8a701b /src/mainboard/system76/oryp5/devicetree.cb | |
| parent | 1fd4d76043ca66be134dad16a8ba67ae75645ee6 (diff) | |
mb/system76/cannonlake/dt: Use comma separated list for arrays
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.
Don't convert the settings for PCIe root ports as they should stay in
the device scope of them.
While on it, remove superfluous comments related to modified lines.
Change-Id: I92414efc9ddb849ceb8b9c4f0bc564bdbd92773b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78638
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/system76/oryp5/devicetree.cb')
| -rw-r--r-- | src/mainboard/system76/oryp5/devicetree.cb | 40 |
1 files changed, 22 insertions, 18 deletions
diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index 733d020979..f17862f4af 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -75,22 +75,24 @@ chip soc/intel/cannonlake device pci 12.6 off end # GSPI #2 device pci 13.0 off end # Integrated Sensor Hub device pci 14.0 on # USB xHCI - # USB2 - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C/DP - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Right - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Left - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-key RGB - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # 3G/LTE - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint - register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # WLAN/Bluetooth - # USB3 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C/DP - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Right - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Left - register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 3G/LTE + register "usb2_ports" = "{ + [0] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C */ + [1] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C/DP */ + [2] = USB2_PORT_MID(OC_SKIP), /* USB 3 Right */ + [3] = USB2_PORT_MID(OC_SKIP), /* USB 3 Left */ + [4] = USB2_PORT_MID(OC_SKIP), /* Per-key RGB */ + [6] = USB2_PORT_MID(OC_SKIP), /* 3G/LTE */ + [7] = USB2_PORT_MID(OC_SKIP), /* Camera */ + [9] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */ + [13] = USB2_PORT_MID(OC_SKIP), /* WLAN/Bluetooth */ + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C/DP */ + [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3 Right */ + [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3 Left */ + [6] = USB3_PORT_DEFAULT(OC_SKIP), /* 3G/LTE */ + }" end device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Shared SRAM @@ -113,8 +115,10 @@ chip soc/intel/cannonlake device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on # SATA - register "SataPortsEnable[1]" = "1" # SSD (SATA1A) - register "SataPortsEnable[4]" = "1" # HDD (SATA4) + register "SataPortsEnable" = "{ + [1] = 1, /* SSD (SATA1A) */ + [4] = 1, /* HDD (SATA4) */ + }" end device pci 19.0 off end # I2C #4 device pci 19.1 off end # I2C #5 |