summaryrefslogtreecommitdiff
path: root/src/mainboard/system76/oryp5/board_info.txt
diff options
context:
space:
mode:
authorTony Huang <tony-huang@quanta.corp-partner.google.com>2024-06-25 15:57:44 +0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2024-06-25 21:56:52 +0000
commitc7c8cf2edd713fd578423bc043403ae4f91e2e29 (patch)
treec766503f47805cc32e03491fd8593348f32bc68a /src/mainboard/system76/oryp5/board_info.txt
parent516d05f43dad59a2ea5ac8b005394011b2f908d4 (diff)
soc/intel/common: Extend WAIT_FOR_DP_MODE_ENTRY_TIMEOUT_MS to 1500ms
Some dongles require more time to be ready, this CL extedns the DP mode entry timeout from 0.5s to 1.5s and make sure the tested dongle display works. Before: [WARN ] DP not ready after 500ms. Abort. After: [INFO ] DP ready after 1211 ms BUG=b:348309582 TEST=emerge coreboot verify tested dongles and monitors display works Change-Id: I22d7800b50f6f7de9f147ae6998a5015d0dc0be9 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83206 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/system76/oryp5/board_info.txt')
0 files changed, 0 insertions, 0 deletions