diff options
| author | Tim Crawford <tcrawford@system76.com> | 2022-07-26 13:47:15 -0600 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-08-12 17:09:53 +0000 |
| commit | a8cf2f2d736172b7c7e88624f1439886ced5ecf4 (patch) | |
| tree | a789499c83a8576195456185b98cb9432a0a518d /src/mainboard/system76/gaze16/variants/gaze16-3050/overridetree.cb | |
| parent | da10c48eb7b765e6be2189c1a990e35161886b6c (diff) | |
mb/system76/gaze16: Rename variant dir
Use the actual model name for the variant dir.
Change-Id: I199b8efb5c3cddb8943ba4b761546caa11c67a30
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/mainboard/system76/gaze16/variants/gaze16-3050/overridetree.cb')
| -rw-r--r-- | src/mainboard/system76/gaze16/variants/gaze16-3050/overridetree.cb | 75 |
1 files changed, 75 insertions, 0 deletions
diff --git a/src/mainboard/system76/gaze16/variants/gaze16-3050/overridetree.cb b/src/mainboard/system76/gaze16/variants/gaze16-3050/overridetree.cb new file mode 100644 index 0000000000..32f0805ac0 --- /dev/null +++ b/src/mainboard/system76/gaze16/variants/gaze16-3050/overridetree.cb @@ -0,0 +1,75 @@ +chip soc/intel/tigerlake + device domain 0 on + subsystemid 0x1558 0x5015 inherit + + device ref peg1 on + # PCIe PEG2 (remapped to PEG1 by FSP) x8, Clock 0 (DGPU) + register "PcieClkSrcUsage[0]" = "0x42" + register "PcieClkSrcClkReq[0]" = "0" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH + register "enable_delay_ms" = "16" + register "enable_off_delay_ms" = "4" + register "reset_delay_ms" = "10" + register "reset_off_delay_ms" = "4" + register "srcclk_pin" = "0" # GFX_CLKREQ0# + device generic 0 on end + end + end + device ref peg0 on + # PCIe PEG0 x4, Clock 4 (SSD2) + register "PcieClkSrcUsage[4]" = "0x40" + register "PcieClkSrcClkReq[4]" = "4" + end + device ref south_xhci on + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Right) + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.2 Gen 2 Type C (Right) + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Left) + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 (Left) + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 (Right) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 Type C (Right) + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 Type C (Right) + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Left) + end + device ref sata on + register "SataPortsEnable[0]" = "1" # HDD (SATA0B) + register "SataPortsEnable[1]" = "1" # SSD1 (SATA1A) + end + device ref pcie_rp5 on + # PCIe root port #5 x1, Clock 5 (GLAN) + register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieClkSrcUsage[5]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + end + device ref pcie_rp7 on + # PCIe root port #7 x1, Clock 7 (CARD) + register "PcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + register "PcieClkSrcUsage[7]" = "6" + register "PcieClkSrcClkReq[7]" = "7" + end + device ref pcie_rp8 on + # PCIe root port #8 x1, Clock 8 (WLAN) + register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" + register "PcieClkSrcUsage[8]" = "7" + register "PcieClkSrcClkReq[8]" = "8" + register "PcieRpSlotImplemented[7]" = "1" + end + device ref pcie_rp9 on + # PCIe root port #9 x4, Clock 9 (SSD1) + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[9]" = "8" + register "PcieClkSrcClkReq[9]" = "9" + register "PcieRpSlotImplemented[8]" = "1" + end + end +end |