soc/intel/tigerlake: add devicetree option PcieRpSlotImplemented

Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI
bit set for any slots of already existing boards, add set the option
PcieRpSlotImplemented=1 where appropriate.

Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

1 files changed, 2 insertions, 0 deletions

diff --git a/src/mainboard/system76/gaze16/variants/3050/overridetree.cb b/src/mainboard/system76/gaze16/variants/3050/overridetree.cb
index 73520b5dc8..c26b7d2fed 100644
--- a/src/mainboard/system76/gaze16/variants/3050/overridetree.cb
+++ b/src/mainboard/system76/gaze16/variants/3050/overridetree.cb
@@ -62,6 +62,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[7]" = "1"
 			register "PcieClkSrcUsage[8]" = "7"
 			register "PcieClkSrcClkReq[8]" = "8"
+			register "PcieRpSlotImplemented[7]" = "1"
 		end
 		device ref pcie_rp9 on
 			# PCIe root port #9 x4, Clock 9 (SSD1)
@@ -69,6 +70,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[8]" = "1"
 			register "PcieClkSrcUsage[9]" = "8"
 			register "PcieClkSrcClkReq[9]" = "9"
+			register "PcieRpSlotImplemented[8]" = "1"
 		end
 	end
 end