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authorFelix Singer <felixsinger@posteo.net>2023-10-26 15:02:46 +0200
committerFelix Singer <service+coreboot-gerrit@felixsinger.de>2023-10-30 14:00:37 +0000
commitd163253ba047515e3317e9da38aa7cc5714a7f0c (patch)
tree0c0c7148194fb268d1ed23159df08f444c8a701b /src/mainboard/system76/bonw14
parent1fd4d76043ca66be134dad16a8ba67ae75645ee6 (diff)
mb/system76/cannonlake/dt: Use comma separated list for arrays
In order to improve the readability of the settings, use a comma separated list to assign values to their indexes instead of repeating the option name for each index. Don't convert the settings for PCIe root ports as they should stay in the device scope of them. While on it, remove superfluous comments related to modified lines. Change-Id: I92414efc9ddb849ceb8b9c4f0bc564bdbd92773b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78638 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/system76/bonw14')
-rw-r--r--src/mainboard/system76/bonw14/devicetree.cb44
1 files changed, 24 insertions, 20 deletions
diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb
index 59a1c14cea..d79aa76659 100644
--- a/src/mainboard/system76/bonw14/devicetree.cb
+++ b/src/mainboard/system76/bonw14/devicetree.cb
@@ -73,23 +73,25 @@ chip soc/intel/cannonlake
device pci 12.6 off end # GSPI #2
device pci 13.0 off end # Integrated Sensor Hub
device pci 14.0 on # USB xHCI
- # USB2
- register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_2
- register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_1
- register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_4
- register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_3
- register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-key RGB
- register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB Type-C
- register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # XFI
- register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
- register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Light guide
- register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
- register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
- # USB3
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_2
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # ANX7440
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_4
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_3
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MID(OC_SKIP), /* USB 3_2 */
+ [1] = USB2_PORT_MID(OC_SKIP), /* USB 3_1 */
+ [2] = USB2_PORT_MID(OC_SKIP), /* USB 3_4 */
+ [3] = USB2_PORT_MID(OC_SKIP), /* USB 3_3 */
+ [4] = USB2_PORT_MID(OC_SKIP), /* Per-key RGB */
+ [5] = USB2_PORT_TYPE_C(OC_SKIP), /* USB Type-C */
+ [6] = USB2_PORT_MID(OC_SKIP), /* XFI */
+ [7] = USB2_PORT_MID(OC_SKIP), /* Camera */
+ [8] = USB2_PORT_MID(OC_SKIP), /* Light guide */
+ [9] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */
+ [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
+ }"
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3_2 */
+ [1] = USB3_PORT_DEFAULT(OC_SKIP), /* ANX7440 */
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3_4 */
+ [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3_3 */
+ }"
end
device pci 14.2 on end # Shared SRAM
device pci 14.3 on # CNVi wifi
@@ -119,9 +121,11 @@ chip soc/intel/cannonlake
device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on # SATA
- register "SataPortsEnable[1]" = "1" # SATA1A (SSD)
- register "SataPortsEnable[3]" = "1" # SATA3 (M.2_SATA3)
- register "SataPortsEnable[4]" = "1" # SATA4 (SSD2)
+ register "SataPortsEnable" = "{
+ [1] = 1, /* SATA1A (SSD) */
+ [3] = 1, /* SATA3 (M.2_SATA3) */
+ [4] = 1, /* SATA4 (SSD2) */
+ }"
end
device pci 19.2 off end # UART #2
device pci 1a.0 off end # eMMC