diff options
| author | Tim Crawford <tcrawford@system76.com> | 2023-06-27 15:47:19 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-03 12:58:43 +0000 |
| commit | 56c09fb5fda0146d7d343fdb3bb27904458bdd07 (patch) | |
| tree | 8cf3534741a03b55ccde26a426e00ee669a3258e /src/mainboard/system76/adl | |
| parent | 10d2af04e754d94b7f6ece11f3e1d5efe07ba59f (diff) | |
mb/system76/{adl,tgl}: Add FMD files
Replace `CBFS_SIZE` with FMD files to declare regions and sizes. This
will be used to lock BIOS region (except SMMSTORE) on boot.
`CBFS_SIZE` was incorrectly set to 10 MiB, so this also corrects the
BIOS region size to match the FIT values.
Change-Id: I0f068f4d9b376f12b46faa5bb0c6a08e6cb744d8
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76155
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Diffstat (limited to 'src/mainboard/system76/adl')
| -rw-r--r-- | src/mainboard/system76/adl/Kconfig | 6 | ||||
| -rw-r--r-- | src/mainboard/system76/adl/board.fmd | 15 |
2 files changed, 18 insertions, 3 deletions
diff --git a/src/mainboard/system76/adl/Kconfig b/src/mainboard/system76/adl/Kconfig index f4fadc300e..49a7b2b226 100644 --- a/src/mainboard/system76/adl/Kconfig +++ b/src/mainboard/system76/adl/Kconfig @@ -98,15 +98,15 @@ config MAINBOARD_VERSION default "oryp9" if BOARD_SYSTEM76_ORYP9 default "oryp10" if BOARD_SYSTEM76_ORYP10 -config CBFS_SIZE - default 0xA00000 - config CONSOLE_POST default y config DIMM_SPD_SIZE default 512 +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" + config ONBOARD_VGA_IS_PRIMARY default y diff --git a/src/mainboard/system76/adl/board.fmd b/src/mainboard/system76/adl/board.fmd new file mode 100644 index 0000000000..f50c357d91 --- /dev/null +++ b/src/mainboard/system76/adl/board.fmd @@ -0,0 +1,15 @@ +FLASH 32M { + SI_DESC 4K +#if CONFIG_MAINBOARD_USES_IFD_GBE_REGION + SI_GBE 8K +#endif + SI_ME 4824K + SI_BIOS@16M 16M { + RW_MRC_CACHE 64K + SMMSTORE(PRESERVE) 256K + WP_RO { + FMAP 4K + COREBOOT(CBFS) + } + } +} |