diff options
| author | Felix Singer <felixsinger@posteo.net> | 2023-06-16 01:33:25 +0200 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2023-06-20 14:33:43 +0000 |
| commit | 743242b4aa3415769fc4f0e1ccdc13893aa2582d (patch) | |
| tree | cf9d21e55bb2f4bafca4f492510602436ddba4f6 /src/mainboard/supermicro | |
| parent | bafe55c36fec131c4b2512ba908aa0fbeb3f5ae3 (diff) | |
treewide,intel/skylake: Use boolean type for s0ix_enable dt option
Using the boolean type and the true/false macros give the reader a
better understanding about the option. Thus, use the bool type for the
attribute and use the macros for assignments.
Skylake mainboards which use that option were changed by the following
command ran from the root directory.
socs="SOC_INTEL_(SKYLAKE|KABYLAKE|SKYLAKE_LGA1151_V2)" && \
option="s0ix_enable" && \
grep -Er "${socs}" src/mainboard | \
cut -d ':' -f 1 | \
awk -F '[/]' '{print $1"/"$2"/"$3"/"$4}' | \
xargs grep -r "${option}" | \
cut -d ':' -f 1 | \
xargs sed -i'' -e "s/${option}\".*\=.*\"1\"/${option}\" \= true/g"
Change-Id: I372dfb65e6bbfc79c3f036ce34bc399875d5ff16
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75871
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/mainboard/supermicro')
| -rw-r--r-- | src/mainboard/supermicro/x11-lga1151-series/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index b4a08bf418..76f75800b3 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -20,7 +20,7 @@ chip soc/intel/skylake register "serirq_mode" = "SERIRQ_CONTINUOUS" # Enabling SLP_S0, SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch - register "s0ix_enable" = "1" + register "s0ix_enable" = true register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" |