diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-07-30 14:07:15 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-18 17:14:48 +0100 |
| commit | 0122afb6093849102caa9662ac14380a41cfb094 (patch) | |
| tree | d56b9de53c5354f22f48bc7ed1990f1280ae1405 /src/mainboard/supermicro | |
| parent | 631c8a269006bb8f02860606d35f8d6590954f5e (diff) | |
cpu/amd/fam10h-fam15h: Update Fam15h APIC config and startup sequence
This fixes Family 15h multiple package support; the previous code
hung in CAR setup and romstage when more than one CPU package was
installed for a variety of loosely related reasons.
TEST: Booted ASUS KGPE-D16 with two Opteron 6328 processors
and several different RDIMM configurations.
Change-Id: I171197c90f72d3496a385465937b7666cbf7e308
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12020
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/mainboard/supermicro')
| -rw-r--r-- | src/mainboard/supermicro/h8dmr_fam10/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/supermicro/h8qme_fam10/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/supermicro/h8scm_fam10/romstage.c | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index c29470f766..bf5093f417 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -167,7 +167,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); + start_other_cores(bsp_apicid); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index eacc87f925..13a101185c 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -234,7 +234,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); + start_other_cores(bsp_apicid); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 6e34f0ac88..7312683fc0 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -158,7 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); + start_other_cores(bsp_apicid); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif |