diff options
author | Jonathan A. Kollasch <jakllsch@kollasch.net> | 2020-01-10 13:23:02 -0600 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-04-14 10:02:24 +0000 |
commit | 3e4f7a39f8cbdfc7cd097b5c57c43f52d9b0fb4c (patch) | |
tree | e11bf81aa69d5efb6afd1f4ce3c0b098f6cf47bb /src/mainboard/supermicro/x9scl/dsdt.asl | |
parent | dd662870dd9da0be937c593b0b62f3b5c8030cf7 (diff) |
mainboard: add Supermicro X9SCL/X9SCM
Boots to Linux.
Works:
- CPU (Core i3-2120 tested)
- Memory (one 1GB 1Rx8 PC3-10600E module tested)
- Slots 4, 6, 7
To fix/improve:
- SuperIO hardware monitor setup for PECI and fan control
- SuperIO ASL in DSDT (e.g. UART Devices)
- PEG PCIe lanes (should show x8 max width instead of x16 on 0:1.0 for Slot 7)
Untested:
- IPMI where BMC is fully implemented (X9SC[LM](+)-F variants)
- GbE on X9SCL+-F (where there are two 82574L instead of one)
- Slot 5 (x4 on 0:06.0) (only applicable to X9SCM variants)
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Change-Id: I985db89d67de21bbafbdc34d7044496434a6eb17
Depends-On: I5b7599746195cfa996a48320404a8dbe6820483a, I1206746332c9939a78b67e7b48d3098bdef8a2ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38346
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/supermicro/x9scl/dsdt.asl')
-rw-r--r-- | src/mainboard/supermicro/x9scl/dsdt.asl | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/src/mainboard/supermicro/x9scl/dsdt.asl b/src/mainboard/supermicro/x9scl/dsdt.asl new file mode 100644 index 0000000000..b6c8930cb6 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/dsdt.asl @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT Revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20171231 /* OEM Revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + Device (PCIB) + { + Name (_ADR, 0x001E0000) + Name (_PRW, Package(){ 13, 4 }) + Method (_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0003ffff, 0, 0, 0x17 }, + }) + } + Return (Package() { + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + }) + } + } + } + + Scope (\_SB.PCI0.PEGP.DEV0) + { + Name (_SUN, 7) + } + + Scope (\_SB.PCI0.PEG1.DEV0) + { + Name (_SUN, 6) + } + + Scope (\_SB.PCI0.PEG6.DEV0) + { + Name (_SUN, 5) + } + + Scope (\_SB.PCI0.RP01) + { + Device (DEV0) + { + Name (_ADR, 0x00000000) + Name (_SUN, 4) + } + } +} |