diff options
| author | Bill XIE <persmule@hardenedlinux.org> | 2021-08-26 19:12:13 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-05 20:37:50 +0000 |
| commit | d00febc99bd83be74e6f1d2386e36eea5051578b (patch) | |
| tree | 12f9c013e5826d557e84e7bb39a3e1dc3dd21a0f /src/mainboard/supermicro/x9sae/early_init.c | |
| parent | 957857de6afb1f4e1431edc6b3f0ef5c7a60542f (diff) | |
mb/supermicro: Add X9SAE and X9SAE-V
Mainboard information can be found in the included documentation.
Change-Id: I9dfc58bb99e14cd9dac2ac53afc0ea11d2252aa9
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/supermicro/x9sae/early_init.c')
| -rw-r--r-- | src/mainboard/supermicro/x9sae/early_init.c | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/src/mainboard/supermicro/x9sae/early_init.c b/src/mainboard/supermicro/x9sae/early_init.c new file mode 100644 index 0000000000..7e032120bc --- /dev/null +++ b/src/mainboard/supermicro/x9sae/early_init.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0xc8); + pnp_write_config(GLOBAL_DEV, 0x1b, 0x6d); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x83); + pnp_write_config(GLOBAL_DEV, 0x24, 0x24); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2b, 0x02); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x80); + + /* Power RAM in S3 */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + pnp_set_logical_device(SERIAL_DEV); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} |