diff options
| author | Bill XIE <persmule@hardenedlinux.org> | 2021-08-26 19:12:13 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-05 20:37:50 +0000 |
| commit | d00febc99bd83be74e6f1d2386e36eea5051578b (patch) | |
| tree | 12f9c013e5826d557e84e7bb39a3e1dc3dd21a0f /src/mainboard/supermicro/x9sae/acpi/pci.asl | |
| parent | 957857de6afb1f4e1431edc6b3f0ef5c7a60542f (diff) | |
mb/supermicro: Add X9SAE and X9SAE-V
Mainboard information can be found in the included documentation.
Change-Id: I9dfc58bb99e14cd9dac2ac53afc0ea11d2252aa9
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/supermicro/x9sae/acpi/pci.asl')
| -rw-r--r-- | src/mainboard/supermicro/x9sae/acpi/pci.asl | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/src/mainboard/supermicro/x9sae/acpi/pci.asl b/src/mainboard/supermicro/x9sae/acpi/pci.asl new file mode 100644 index 0000000000..72b497c2ef --- /dev/null +++ b/src/mainboard/supermicro/x9sae/acpi/pci.asl @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// Intel PCI to PCI bridge 0:1e.0 + +Device (PCIB) +{ + Name (_ADR, 0x001E0000) // _ADR: Address + Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake + + Method (_PRT) // _PRT: PCI Interrupt Routing Table + { + If (PICM) { + Return (Package() { + Package() { 0x0001ffff, 0, 0, 0x16 }, + Package() { 0x0001ffff, 1, 0, 0x15 }, + Package() { 0x0001ffff, 2, 0, 0x14 }, + Package() { 0x0001ffff, 3, 0, 0x13 }, + Package() { 0x0002ffff, 0, 0, 0x12 }, + Package() { 0x0002ffff, 1, 0, 0x13 }, + Package() { 0x0002ffff, 2, 0, 0x11 }, + Package() { 0x0002ffff, 3, 0, 0x10 }, + Package() { 0x0003ffff, 0, 0, 0x13 }, + Package() { 0x0003ffff, 1, 0, 0x12 }, + Package() { 0x0003ffff, 2, 0, 0x15 }, + Package() { 0x0003ffff, 3, 0, 0x16 }, + Package() { 0x0000ffff, 0, 0, 0x10 }, + Package() { 0x0000ffff, 1, 0, 0x11 }, + Package() { 0x0000ffff, 2, 0, 0x12 }, + Package() { 0x0000ffff, 3, 0, 0x13 }, + }) + } + Return (Package() { + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKE, 0 }, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + }) + } +} |